Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99)最新文献_第5页

Testable and fault tolerant design for FFT networks FFT网络的可测试和容错设计

Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99) Pub Date : 1999-11-01 DOI: 10.1109/DFTVS.1999.802886

Jin-Fu Li, Cheng-Wen Wu

引用次数: 2

Reconfiguration of one-time programmable FPGAs with faulty logic resources 具有错误逻辑资源的一次性可编程fpga的重新配置

Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99) Pub Date : 1999-11-01 DOI: 10.1109/DFTVS.1999.802904

Wenyi Feng, Xiao-Tao Chen, F. Meyer, F. Lombardi

{"title":"Reconfiguration of one-time programmable FPGAs with faulty logic resources","authors":"Wenyi Feng, Xiao-Tao Chen, F. Meyer, F. Lombardi","doi":"10.1109/DFTVS.1999.802904","DOIUrl":"https://doi.org/10.1109/DFTVS.1999.802904","url":null,"abstract":"A comprehensive approach is given to reconfigure field programmable gate arrays (FPGAs) with faults in the logic resources. Reconfiguration consists of a reassignment of the cells that takes into account the one-time programmable nature of the chip resources. The method alters neither the FPGA nor the fault-free design; so the effectiveness of the reassignment depends on the efficient use of routing resources in the fault-free design. Under a generalized architecture, the spare routing resources needed are obtained to bypass each faulty cell and reassign its functions to a spare (unused) cell. If every channel has as many spare trades as half the number of logic cell inputs and outputs, then any single faulty cell can be reassigned, thus yielding a successful chip reconfiguration. The proposed reassignment algorithm has an efficient execution, so it can be run while chips are programmed and tested on an assembly line. The number of calls to the routing software is at worst quadratic in the number of faulty cells, provided no backtracking is needed in the reassignment. Under some randomness assumptions, the average number of calls to the routing software is linear in the number of faulty cells. The proposed method is analyzed with benchmark circuits and simulation results are presented.","PeriodicalId":448322,"journal":{"name":"Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131330478","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Creating 35 mm camera active pixel sensors 创建35毫米相机有源像素传感器

Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99) Pub Date : 1999-11-01 DOI: 10.1109/DFTVS.1999.802865

G. Chapman, Y. Audet

引用次数: 16

Power consumption in fast dividers using time shared TMR 使用分时TMR的快速分压器的功耗

Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99) Pub Date : 1999-11-01 DOI: 10.1109/DFTVS.1999.802892

W. Gallagher, E. Swartzlander

引用次数: 2

Fast signature simulation for PPSFP simulators PPSFP模拟器的快速签名仿真

Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99) Pub Date : 1999-11-01 DOI: 10.1109/DFTVS.1999.802884

F. Khadour, Xiaoling Sun

引用次数: 0