Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99)最新文献_第3页

Fault-tolerant refresh power reduction of DRAMs for quasi-nonvolatile data retention 准非易失性数据保留的dram容错刷新功率降低

Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99) Pub Date : 1999-11-01 DOI: 10.1109/DFTVS.1999.802898

Y. Katayama, E. Stuckey, S. Morioka, Z. Wu

{"title":"Fault-tolerant refresh power reduction of DRAMs for quasi-nonvolatile data retention","authors":"Y. Katayama, E. Stuckey, S. Morioka, Z. Wu","doi":"10.1109/DFTVS.1999.802898","DOIUrl":"https://doi.org/10.1109/DFTVS.1999.802898","url":null,"abstract":"A quasi-nonvolatile memory system based on commercially available low-power dynamic random access memory (DRAM) technology is proposed and demonstrated. By applying a powerful one-shot Reed-Solomon error correction code (ECC) to the data stored in the DRAM, the refresh rate and memory system power usage can be greatly reduced while still maintaining data integrity. An adaptive refresh rate controller was developed in order to ensure robustness against the variations in data retention time due to perturbation effects such as DRAM part-to-part variations, environmental changes and data pattern sensitivity, while at the same time minimizing power usage. By checking for data failures among a small subset of data bits which are dynamically selected at the beginning of each use of the system, the state of the perturbation effects are predicted and used to adjust the refresh rate. As a result, a system was developed that provides reliability equivalent to standard DRAM systems while greatly (10-100X) reducing the refresh power. Experimental results of a test system are presented.","PeriodicalId":448322,"journal":{"name":"Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117283101","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 31

Charge sharing fault detection for CMOS domino logic circuits CMOS多米诺逻辑电路的电荷共享故障检测

Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99) Pub Date : 1999-11-01 DOI: 10.1109/DFTVS.1999.802872

Ching-Hwa Cheng, Shih-Chieh Chang, Jinn-Shyan Wang, W. Jone

{"title":"Charge sharing fault detection for CMOS domino logic circuits","authors":"Ching-Hwa Cheng, Shih-Chieh Chang, Jinn-Shyan Wang, W. Jone","doi":"10.1109/DFTVS.1999.802872","DOIUrl":"https://doi.org/10.1109/DFTVS.1999.802872","url":null,"abstract":"Because domino logic design offers smaller area and higher speed than conventional CMOS design, it is very popular in high performance processor design. However, domino logic suffers from several design problems and one of the most notable is the charge sharing problem. In domino logic, there are two operations: the pre-charge phase and the evaluation phase. The charge sharing problem occurs when the charge which is stored at the output node in the pre-charge phase is shared among the junction capacitance of transistors in the evaluation phase. Charge sharing may degrade the output voltage level or even cause an erroneous output value. In this paper, we describe a method to measure the sensitivity of the charge sharing problem for a domino gate. For each domino gate, we compute a value called CS-vulnerability which describes the degree of sensitivity for a domino gate to have the charge sharing problem. In addition, our algorithm also generates test vectors to activate the worst case of the charge sharing problem. We have performed experiments on a large set of MCNC benchmark circuits.","PeriodicalId":448322,"journal":{"name":"Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99)","volume":"259 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116060516","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 19

Time-shared modular redundancy for fault-tolerant FFT processors 容错FFT处理器的分时模块化冗余

Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99) Pub Date : 1999-11-01 DOI: 10.1109/DFTVS.1999.802893

V. Piuri, E. Swartzlander

引用次数: 2

Low power dissipation in BIST schemes for modified Booth multipliers 改进的Booth乘法器的BIST方案的低功耗

Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99) Pub Date : 1999-11-01 DOI: 10.1109/DFTVS.1999.802877

X. Kavousianos, D. Bakalis, H. T. Vergos, D. Nikolos, G. Alexiou

引用次数: 10

Failure tests on 64 Mb SDRAM in radiation environment 辐射环境下64mb SDRAM的失效测试

Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99) Pub Date : 1999-11-01 DOI: 10.1109/DFTVS.1999.802881

S. Bertazzoni, G. Cardarilli, D. Piergentili, M. Salmeri, A. Salsano, D. D. Giovenale, G. C. Grande, P. Marinucci, S. Sperandei, S. Bartalucci, G. Mazzenga, M. Ricci, V. Bidoli, D. D. Francesco, P. Picozza, A. Rovelli

{"title":"Failure tests on 64 Mb SDRAM in radiation environment","authors":"S. Bertazzoni, G. Cardarilli, D. Piergentili, M. Salmeri, A. Salsano, D. D. Giovenale, G. C. Grande, P. Marinucci, S. Sperandei, S. Bartalucci, G. Mazzenga, M. Ricci, V. Bidoli, D. D. Francesco, P. Picozza, A. Rovelli","doi":"10.1109/DFTVS.1999.802881","DOIUrl":"https://doi.org/10.1109/DFTVS.1999.802881","url":null,"abstract":"In this paper we analyze the failures of Commercial Off The Shelf (COTS) 64 Mb Synchronous DRAM (SDRAM) in a radiation environment. The experimental setup, the test procedure, and the results of three different test runs at the Catania LNS-INFN cyclotron are described in some detail. Three kinds of heavy ions were used to test devices under different conditions of energy release that generates different amount of charge inside the chip. In particular, 30 MeV/AMU /sup 93/Nb (LET/sub Si//spl sim/21 MeV/(mg/cm/sup 2/), R/sub Si//spl sim/397 /spl mu/m), 30 MeV/AMU /sup 120/Sn (LET/sub Si//spl sim/30 MeV/(mg/cm/sup 2/), R/sub Si//spl sim/370 /spl mu/m) and 15 MeV/AMU /sup 197/Au (LET/sub Si//spl sim/90 MeV/(mg/cm/sup 2/), R/sub Si//spl sim/95 /spl mu/m) were used. In all cases, the bare dies were directly bonded on an AF4 carrier to avoid plastic and lead-frame shielding. Different failure types that could affect the operations of a system based on this device were registered. To verify that the characteristics of the events depend on the zone struck by the particle, a specific test was performed.","PeriodicalId":448322,"journal":{"name":"Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99)","volume":"27 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123574397","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

Testing for path delay faults using test points 使用测试点测试路径延迟故障

Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99) Pub Date : 1999-11-01 DOI: 10.1109/DFTVS.1999.802873

S. Tragoudas, N. Denny

引用次数: 11

Algorithms for efficient runtime fault recovery on diverse FPGA architectures 在不同FPGA架构上有效的运行时故障恢复算法

Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99) Pub Date : 1999-11-01 DOI: 10.1109/DFTVS.1999.802906

J. Lach, W. Mangione-Smith, M. Potkonjak

引用次数: 28

RAMSES: a fast memory fault simulator RAMSES:快速内存故障模拟器

Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99) Pub Date : 1999-11-01 DOI: 10.1109/DFTVS.1999.802882

Chi-Feng Wu, Chih-Tsun Huang, Cheng-Wen Wu

引用次数: 84

A structural approach for space compaction for sequential circuits 顺序电路空间压缩的一种结构方法

Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99) Pub Date : 1999-11-01 DOI: 10.1109/DFTVS.1999.802889

M. Seuring, M. Gössel

引用次数: 1

A methodology for efficient simulation and diagnosis of mixed-signal systems using error waveforms 一种利用误差波形对混合信号系统进行有效仿真和诊断的方法

Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99) Pub Date : 1999-11-01 DOI: 10.1109/DFTVS.1999.802903

S. Cherubal, A. Chatterjee

引用次数: 1