Time-shared modular redundancy for fault-tolerant FFT processors

Abstract

This paper presents an efficient approach to concurrent error detection and correction for FFT processors by using time-shared modular redundancy. Digits of each input operand are partitioned in disjoint subsets: the nominal operations are performed more than once on each subset by using different arithmetic units. Comparison of results allows detection and, possibly, correction of errors. The modified architectures for detection and correction are analyzed and evaluated.