Algorithms for efficient runtime fault recovery on diverse FPGA architectures

Abstract

The inherent redundancy and in-the-field reconfiguration capabilities of field programmable gate arrays (FPGAs) provide alternatives to integrated circuit redundancy-based fault recovery techniques. An algorithm for efficient runtime recovery from permanent logic faults in the Xilinx 4000 architecture has been expanded to include interconnect fault recovery and has been applied to a diverse set of FPGA architectures. The post-fault-detection system downtime is minimized, and the end user need not have access to computer-aided design (CAD) tools, making the algorithm completely transparent to system users. Although some architectural features allow for a more efficient implementation, high levels of fault recovery with low timing and resource overhead can be achieved on these diverse architectures.