Novel control pattern generators for interconnect testing with boundary scan

Abstract

We give a comprehensive model of interconnect testing in boundary scan architectures. This includes two fault categories: driver faults (stuck-at, stuck-driving, and stuck-not-driving (equivalent to stuck-open)) and net faults (shorts). We permit short faults to exhibit zero-dominance (wired-AND), one-dominance (wired-OR), and net-dominance. We split the built-in self-test hardware into two components: a control pattern test generator (CTPG) and a data pattern test generator (DTPG). For the DTPG, we use a complementary counting sequence, which is an instance of a maximal independent test set. We give novel designs for CTPGs that guarantee 100% fault coverage with low hardware overhead and time complexity. We give a general and complete procedure to implement the CTPGs. Using a linear feedback shift register as a one-shot counter to cover all control cells in the boundary scan, we ensure that no two control cells of one net are assigned to a single register; this avoids circuit damage when testing.