MICRO 17Pub Date : 1984-12-01DOI: 10.1145/800016.808218
Christos A. Papachriston, J. Reuter
{"title":"Microassembly and area reduction techniques for PLA microcode","authors":"Christos A. Papachriston, J. Reuter","doi":"10.1145/800016.808218","DOIUrl":"https://doi.org/10.1145/800016.808218","url":null,"abstract":"This paper presents new techniques for generating PLA microcode with the overall goal of implementing functions or algorithms in VLSI. The microcode is appropriate for PLA-based microarchitectures with powerful sequencing capabilities already proposed. A microassembly language is introduced with unusual flexibility for conditional field assembly and capability to support microarchitectures based on PLA stores An important contribution of this work is an area reduction algorithm for PLA microcode based on a breadth-first graph searching approach. Experimental results provided demonstrate the viability and usefulness of the proposed technique for designing PLA firmware in a VLSI environment.","PeriodicalId":447708,"journal":{"name":"MICRO 17","volume":"151 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115314303","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
MICRO 17Pub Date : 1984-12-01DOI: 10.1145/800016.808231
T. Dobry, Y. Patt, A. Despain
{"title":"Design decisions influencing the microarchitecture for a Prolog machine","authors":"T. Dobry, Y. Patt, A. Despain","doi":"10.1145/800016.808231","DOIUrl":"https://doi.org/10.1145/800016.808231","url":null,"abstract":"The PLM-1 is the first step in the hardware implementation of a heterogeneous MIMD processor for logic programming. This paper describes its ISP architecture, and discusses in detail some of the design decisions relative to its microarchitecture.","PeriodicalId":447708,"journal":{"name":"MICRO 17","volume":"147 11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129894484","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
MICRO 17Pub Date : 1984-12-01DOI: 10.1145/800016.808217
B. Su, S. Ding, Lan Jin
{"title":"An improvement of trace scheduling for global microcode compaction","authors":"B. Su, S. Ding, Lan Jin","doi":"10.1145/800016.808217","DOIUrl":"https://doi.org/10.1145/800016.808217","url":null,"abstract":"Fisher's trace scheduling procedure for global compaction has proven to be able to produce significant reduction in execution time of compacted microcode, however extra space may be sometimes required during bookkeeping, and the efficacy of compaction of microprogram loop is lower than that of hand compaction.\u0000 This paper introduces an improved trace scheduling compaction algorithm to mitigate the drawbacks mentioned above. The improved algorithm is based on a modified menu of moving microoperations, an improved trace scheduling algorithm, and a special loop compaction algorithm. Preliminary tests indicate that this global compaction algorithm gives shorter execution time and less space requirement in comparison with Fisher's algorithm.","PeriodicalId":447708,"journal":{"name":"MICRO 17","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115270088","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
MICRO 17Pub Date : 1984-12-01DOI: 10.1145/800016.808225
Juha-Matti Heimonen, J. Heinänen
{"title":"Migration implementation by integrating microprogramming and HLL programming","authors":"Juha-Matti Heimonen, J. Heinänen","doi":"10.1145/800016.808225","DOIUrl":"https://doi.org/10.1145/800016.808225","url":null,"abstract":"Implementing vertical migrations involves synthesizing new microcoded instructions from selected parts of HLL programs and loading the microcode into the computer's control memory. Ideally, both of these tasks are done automatically so that programs can be written independently of their actual level of implementation. This paper suggests the integration of microprogramming and HLL programming as a step toward the automation of the migration process. A possible linguistic convention for software/firmware interfacing is presented. Compiling of migrated programs is also discussed and examples are given. Finally, an attempt is made to compare the migration effects to those obtainable by automatic synthesis methods.","PeriodicalId":447708,"journal":{"name":"MICRO 17","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126661906","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
MICRO 17Pub Date : 1984-12-01DOI: 10.1145/800016.808232
B. Levy
{"title":"Microcode verification using SDVS-the method and a case study","authors":"B. Levy","doi":"10.1145/800016.808232","DOIUrl":"https://doi.org/10.1145/800016.808232","url":null,"abstract":"This paper describes SDVS (State Delta Verification System), its application to microcode verification, and the verification of a particular example referred to as the H-machine example. The example illustrates how particular microcode that interprets a computer instruction set can be proved correct and how this proof is accomplished with an existing, automated verification system.","PeriodicalId":447708,"journal":{"name":"MICRO 17","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131844075","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
MICRO 17Pub Date : 1984-12-01DOI: 10.1145/800016.808212
John F. Brown, R. L. Sites
{"title":"A chip set microarchitecture for a high-performance VAX implementation","authors":"John F. Brown, R. L. Sites","doi":"10.1145/800016.808212","DOIUrl":"https://doi.org/10.1145/800016.808212","url":null,"abstract":"Fast virtual-address translation and instruction parsing are two hard problems of implementing many modern architectures, including the VAX computer architecture. Meeting the additional constraint of fitting a VAX 11/780-computer-speed implementation into a small number of chips requires a careful coupling of microcode and chip hardware. This paper describes the chip set microarchitecture and the microcode strategies that achieve 11/780 performance. The key features are a VAX instruction prefetch unit occupying one-fourth of a custom NMOS chip, and a memory subsystem occupying another one-fourth of the chip.","PeriodicalId":447708,"journal":{"name":"MICRO 17","volume":"189 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133320354","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
MICRO 17Pub Date : 1984-12-01DOI: 10.1145/800016.808222
Gary Staas
{"title":"TDL: A hardware/microcode test language interpreter","authors":"Gary Staas","doi":"10.1145/800016.808222","DOIUrl":"https://doi.org/10.1145/800016.808222","url":null,"abstract":"TDL is an interpreter for a high level test language used in the development of hardware and microcode. A user can supply commands interactively at a terminal, or from a prepared command file to facilitate automated testing. TDL can communicate to either real hardware or a program simulating the hardware, supplying a uniform interface to both. TDL's features simplify test writing, generating test cases, and calculating test results.","PeriodicalId":447708,"journal":{"name":"MICRO 17","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116169729","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
MICRO 17Pub Date : 1984-12-01DOI: 10.1145/800016.808210
J. Wilkes
{"title":"Architecture of a VLSI multiple ISA emulator","authors":"J. Wilkes","doi":"10.1145/800016.808210","DOIUrl":"https://doi.org/10.1145/800016.808210","url":null,"abstract":"This paper describes the architecture of a microprogrammed processor currently under development that addresses specific program objectives. These objectives include system throughput, ISA flexibility and software transportability. The design project is at the stage of completion of the architecture and the initial stages of VLSI chip design. Three candidate ISAs are scheduled to be implemented in a prototype form in the near future. While it is too early to report on results as they relate to the objectives it is believed that the overall architecture will remain as described.","PeriodicalId":447708,"journal":{"name":"MICRO 17","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127552219","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
MICRO 17Pub Date : 1984-12-01DOI: 10.1145/800016.808234
Kazutoshi Takahashi, E. Takahashi, T. Bitoh, T. Sugimoto
{"title":"A new universal microprogram converter","authors":"Kazutoshi Takahashi, E. Takahashi, T. Bitoh, T. Sugimoto","doi":"10.1145/800016.808234","DOIUrl":"https://doi.org/10.1145/800016.808234","url":null,"abstract":"Following the software crisis, a firmware crisis has occurred.\u0000 Since too much man-power and time is needed to develop microprograms, the ones already produced like software have to be used as long as possible.\u0000 This paper describes a general purpose microprogram conversion tool which is one of the methods used to reduce the man-power and time required for microprogram development and examples of the execution results obtained using this tool.","PeriodicalId":447708,"journal":{"name":"MICRO 17","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115298634","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
MICRO 17Pub Date : 1984-12-01DOI: 10.1145/800016.808209
Jack N. Fenner, J. A. Schmidt, H. A. Halabi, D. Agrawal
{"title":"MASCO: An academic exercise in computer design using microprogramming","authors":"Jack N. Fenner, J. A. Schmidt, H. A. Halabi, D. Agrawal","doi":"10.1145/800016.808209","DOIUrl":"https://doi.org/10.1145/800016.808209","url":null,"abstract":"The design of a host machine architecture for implementing an existing image machine architecture is considered. The proposed microarchitecture uses a microprogrammed control unit to emulate the Motorola MC6809 microprocessor architecture.\u0000 The detailed hardware characteristics of the proposed machine are described and the microinstruction set is defined. The microroutines that emulate the MC6809 instruction set have been developed. A practical implementation using current technology is studied and some realistic timing characteristics are determined. The simulation of the proposed architecture is reviewed and the performance is evaluated. Finally, comparisons with existing models are made and the results are discussed.","PeriodicalId":447708,"journal":{"name":"MICRO 17","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116967136","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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