A chip set microarchitecture for a high-performance VAX implementation

Abstract

Fast virtual-address translation and instruction parsing are two hard problems of implementing many modern architectures, including the VAX computer architecture. Meeting the additional constraint of fitting a VAX 11/780-computer-speed implementation into a small number of chips requires a careful coupling of microcode and chip hardware. This paper describes the chip set microarchitecture and the microcode strategies that achieve 11/780 performance. The key features are a VAX instruction prefetch unit occupying one-fourth of a custom NMOS chip, and a memory subsystem occupying another one-fourth of the chip.