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Design verification of a VLSI VAX microcomputer VLSI VAX微型计算机的设计验证
MICRO 17 Pub Date : 1984-12-01 DOI: 10.1145/800016.808214
S. Samudrala, Charles Lo, John F. Brown, Richard E. Calcagni
{"title":"Design verification of a VLSI VAX microcomputer","authors":"S. Samudrala, Charles Lo, John F. Brown, Richard E. Calcagni","doi":"10.1145/800016.808214","DOIUrl":"https://doi.org/10.1145/800016.808214","url":null,"abstract":"Design verification as part of development provides an opportunity to correct design errors, improve performance characteristics, and optimize hardware. This paper presents the strategy and an overview of the verification performed in the development of a VLSI VAX microcomputer. Using a hierarchical methodology for simulation and verification, the logic design and circuit design have been verified.","PeriodicalId":447708,"journal":{"name":"MICRO 17","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128285349","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Mapping HLL constructs into microcode for improved execution speed 将HLL构造映射到微码中以提高执行速度
MICRO 17 Pub Date : 1984-12-01 DOI: 10.1145/800016.808207
V. Milutinovic, D. Roberts, K. Hwang
{"title":"Mapping HLL constructs into microcode for improved execution speed","authors":"V. Milutinovic, D. Roberts, K. Hwang","doi":"10.1145/800016.808207","DOIUrl":"https://doi.org/10.1145/800016.808207","url":null,"abstract":"A processor architecture is presented which enables the constructs typical of HLLs to be mapped into the constructs typical of microcode. This mapping is provided only for selected HLL primitives and HLL statements with a relatively small number of operands and parameters. We are concerned about the optimal hardware/software trade-off, and not about the absolute 1:1 correspondence between HLL statements and highly horizontal microcode. Still, our approach enables the software for time-critical applications to be entirely written in the HLL and executed in the microcode, without the execution-time deteriorations typical for the systems with a large semantic gap between the HLL architecture and the processor architecture. This approach is particularly suitable for the time-critical dedicated control and signal processing. Using an extended subset of Fortran 77, one that matches the typical demands of the specified application area, it is shown that the proposed architecture supports the mapping of HLL constructs into microinstructions. A flexible register-transfer level simulator has been designed and implemented. It was used to run kernel routines on various configurations of the proposed architecture.","PeriodicalId":447708,"journal":{"name":"MICRO 17","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123497031","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Global methods in the flow graph approach to retargetable microcode generation 流图方法中的全局方法实现可重定向微码生成
MICRO 17 Pub Date : 1984-12-01 DOI: 10.1145/800016.808236
R. A. Mueller, Joseph Varghese, V. Allan
{"title":"Global methods in the flow graph approach to retargetable microcode generation","authors":"R. A. Mueller, Joseph Varghese, V. Allan","doi":"10.1145/800016.808236","DOIUrl":"https://doi.org/10.1145/800016.808236","url":null,"abstract":"We have reported on local retargetable microcode generation methods based on the flow graph model in previous papers. In this paper, we consider the extension of these methods to global retargetable microcode generation. This includes intermediate representations of basic blocks containing control flow directives and their construction from global program dags, resource allocation and its interaction with code generation, machine-independent semantics and procedures for global microcode generation, and global compaction. The emphasis is on issues and promising directions for research on global methods vis a vis final results and definitive answers, as it reflects the early stages of our research.","PeriodicalId":447708,"journal":{"name":"MICRO 17","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121417176","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Sequential Prolog machine: Image and host architectures 顺序Prolog机器:映像和主机体系结构
MICRO 17 Pub Date : 1984-12-01 DOI: 10.1145/800016.808230
E. Tick
{"title":"Sequential Prolog machine: Image and host architectures","authors":"E. Tick","doi":"10.1145/800016.808230","DOIUrl":"https://doi.org/10.1145/800016.808230","url":null,"abstract":"A modified version of D. Warren's sequential Prolog machine architecture is described. Data and instruction formats are given. A microcoded host architecture is also described, with formats and examples presented.","PeriodicalId":447708,"journal":{"name":"MICRO 17","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130101452","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
An axiomatization of low-level parallelism in microarchitectures 微体系结构中低级并行性的公理化
MICRO 17 Pub Date : 1984-12-01 DOI: 10.1145/800016.808240
W. Damm
{"title":"An axiomatization of low-level parallelism in microarchitectures","authors":"W. Damm","doi":"10.1145/800016.808240","DOIUrl":"https://doi.org/10.1145/800016.808240","url":null,"abstract":"This paper presents the heart of a universal syntax-directed proof system for the verification of horizontal computer architectures.\u0000 The system is based on the axiomatic architecture description language AADL, which incorporates a comcise model of clocked microarchitectures. For a given description A of a host architecture, we show how to axiomatize A's microoperations and present powerful proof-rules dealing with the inherent low-level parallelism of horizontal architectures. They allow for a complete axiomatic treatment of the timing behaviour and dynamic conflicts of microprograms written in an A-dependent high-level microprogramming language based on S*.","PeriodicalId":447708,"journal":{"name":"MICRO 17","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133491839","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Applications of pipelining to firmware 流水线到固件的应用
MICRO 17 Pub Date : 1984-12-01 DOI: 10.1145/800016.808211
D. Proulx
{"title":"Applications of pipelining to firmware","authors":"D. Proulx","doi":"10.1145/800016.808211","DOIUrl":"https://doi.org/10.1145/800016.808211","url":null,"abstract":"It has been found that pipelining at the firmware level of machine organization can provide significant execution time benefits for certain types of instructions. The essential concept involved with this approach is the pipelining of operations within the hardware under direct control of the firmware, rather than the pipelining of microinstructions. Specifically, multiple data values exist within the machine's datapaths which have undergone different amounts of processing.\u0000 This paper describes the application of these techniques to a specific pipelined computer. A brief description of the system level pipeline is provided with two examples of the firmware pipeline approach. The operations of floating point normalization and memory transfers have been described in detail.","PeriodicalId":447708,"journal":{"name":"MICRO 17","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127095817","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
The implementation of the attributed recursive descent architecture in VAX-11/780 microcode VAX-11/780微码中属性递归下降结构的实现
MICRO 17 Pub Date : 1984-12-01 DOI: 10.1145/800016.808228
C. Ardoin, J. Linn, B. W. Reynolds
{"title":"The implementation of the attributed recursive descent architecture in VAX-11/780 microcode","authors":"C. Ardoin, J. Linn, B. W. Reynolds","doi":"10.1145/800016.808228","DOIUrl":"https://doi.org/10.1145/800016.808228","url":null,"abstract":"This paper describes a case study in the implementation of a special purpose architecture on a particular microprogrammable engine. The host engine used is the VAX-11/780; the target architecture is one tailored for implementing recursive descent translators. The paper describes the mapping of the target resources onto the host machine including a discussion of the issues involved in interfacing with the normal VAX environment. The architecture specification does not mandate the exact bit-level representation of the target architecture instructions allowing a more efficient emulator to be constructed. Many of the important design decisions involve choosing instruction representations to effectively utilize the host engine. The paper concludes with discussion of the considerable shortcomings of this approach, of the suitability of the VAX-11/780 as an underlying engine for the target architecture, and of the implications of the study for universal host machines.","PeriodicalId":447708,"journal":{"name":"MICRO 17","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127331279","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A survey of resource allocation methods in optimizing microcode compilers 优化微码编译器资源分配方法综述
MICRO 17 Pub Date : 1984-12-01 DOI: 10.1145/800016.808237
R. A. Mueller, M. Duda, Stephen M. O'Haire
{"title":"A survey of resource allocation methods in optimizing microcode compilers","authors":"R. A. Mueller, M. Duda, Stephen M. O'Haire","doi":"10.1145/800016.808237","DOIUrl":"https://doi.org/10.1145/800016.808237","url":null,"abstract":"This paper surveys results reported on resource allocation in optimizing microcode compilers. Resource allocation is the phase of microcode generation that binds variables and operators of program text to machine registers and functional units. The first substantial results on resource allocation in optimizing microcode compilers were reported by DeWitt, and subsequent results were reported by Kim and Tan and by Ma and Lewis. We examine each of these methods, focusing on the assumptions they make, how realistic those assumptions are, the algorithms employed and their foundational basis, the perceived difficulty of implementing the algorithms, their effectiveness, and their computational complexity. We conclude by summarizing the results and pointing out important areas for future research, particularly in the context of flow graph microcode generation.","PeriodicalId":447708,"journal":{"name":"MICRO 17","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129126616","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
SDVS: A system for verifying microcode correctness 用于验证微码正确性的系统
MICRO 17 Pub Date : 1984-12-01 DOI: 10.1145/800016.808233
L. Marcus, S. D. Crocker, J. Landauer
{"title":"SDVS: A system for verifying microcode correctness","authors":"L. Marcus, S. D. Crocker, J. Landauer","doi":"10.1145/800016.808233","DOIUrl":"https://doi.org/10.1145/800016.808233","url":null,"abstract":"This paper is a progress report on an experimental system, the state delta verification system (SDVS), for verifying microcode correctness. The goal of this project is to solve some of the problems, both theoretical and engineering, obstructing the realization of a usable and applicable program for checking proofs of microcode correctness. The ideal result would be a system that could be naturally incorporated into the specification-implementation cycle of, for example, microcoded machine instruction sets.","PeriodicalId":447708,"journal":{"name":"MICRO 17","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130816481","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Logic programming applied to hardware design specification and verification 逻辑编程应用于硬件设计说明和验证
MICRO 17 Pub Date : 1984-12-01 DOI: 10.1145/800016.808239
D. Sidhu
{"title":"Logic programming applied to hardware design specification and verification","authors":"D. Sidhu","doi":"10.1145/800016.808239","DOIUrl":"https://doi.org/10.1145/800016.808239","url":null,"abstract":"This paper proposes the use of logic programming techniques in the specification and verification of hardware designs. Logic programming specifications are formal and directly executable. The advantages of executable specifications are: (1) the specification is itself a prototype of the specified system, (2) incremental development of specifications is possible, (3) behavior exhibited by the specification when executed can be used to check conformity of the specification with requirements. We discuss how Horn clause logic, which has a procedural interpretation, and predicate logic programming language, Prolog, can be used as a hardware description language to specify and verify the correctness of hardware systems. The Prolog system possesses a backtracking mechanism and a powerful pattern-matching feature which is based on unification. A novel feature of the proposed approach is that it can be used to answer interesting questions about a hardware design without resorting to simulation.","PeriodicalId":447708,"journal":{"name":"MICRO 17","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126432107","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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