Architecture of a VLSI multiple ISA emulator

This paper describes the architecture of a microprogrammed processor currently under development that addresses specific program objectives. These objectives include system throughput, ISA flexibility and software transportability. The design project is at the stage of completion of the architecture and the initial stages of VLSI chip design. Three candidate ISAs are scheduled to be implemented in a prototype form in the near future. While it is too early to report on results as they relate to the objectives it is believed that the overall architecture will remain as described.