Microassembly and area reduction techniques for PLA microcode

Abstract

This paper presents new techniques for generating PLA microcode with the overall goal of implementing functions or algorithms in VLSI. The microcode is appropriate for PLA-based microarchitectures with powerful sequencing capabilities already proposed. A microassembly language is introduced with unusual flexibility for conditional field assembly and capability to support microarchitectures based on PLA stores An important contribution of this work is an area reduction algorithm for PLA microcode based on a breadth-first graph searching approach. Experimental results provided demonstrate the viability and usefulness of the proposed technique for designing PLA firmware in a VLSI environment.