发布求助
文献互助 智能选刊 最新文献

[Proceedings] 1991 International Workshop on Defect and Fault Tolerance on VLSI Systems最新文献

筛选
英文 中文
Efficient and optimal fault-to-spare assignments in doubly fault tolerant arrays 双容错阵列中有效和最优的故障备用分配
[Proceedings] 1991 International Workshop on Defect and Fault Tolerance on VLSI Systems Pub Date : 1991-11-18 DOI: 10.1109/DFTVS.1991.199968
N. Shrivastava, R. Melhem
{"title":"Efficient and optimal fault-to-spare assignments in doubly fault tolerant arrays","authors":"N. Shrivastava, R. Melhem","doi":"10.1109/DFTVS.1991.199968","DOIUrl":"https://doi.org/10.1109/DFTVS.1991.199968","url":null,"abstract":"Given a doubly fault tolerant system with m faults, the authors present an algorithm for finding a fault-to-spare assignment for the m faults in O(m) time. This improvement over the O(m/sup 1.5/) bi-partite graph technique for finding an assignment is obtained by partitioning the problem into independent regions and proving that, in each region, an assignment may be found in linear time. The region approach also allows for an efficient solution of a related problem. Namely, finding a fault-to-spare assignment which minimizes the number of uncovered nodes. For two dimensional arrays augmented with one row and one column of spares, such an optimal assignment may be found in linear time.<<ETX>>","PeriodicalId":440536,"journal":{"name":"[Proceedings] 1991 International Workshop on Defect and Fault Tolerance on VLSI Systems","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122929516","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Delay fault simulation of self-checking error checkers 自检纠错器延时故障仿真
[Proceedings] 1991 International Workshop on Defect and Fault Tolerance on VLSI Systems Pub Date : 1991-11-18 DOI: 10.1109/DFTVS.1991.199962
K. Hirabayashi
{"title":"Delay fault simulation of self-checking error checkers","authors":"K. Hirabayashi","doi":"10.1109/DFTVS.1991.199962","DOIUrl":"https://doi.org/10.1109/DFTVS.1991.199962","url":null,"abstract":"A robustly-tested gate-delay fault model is proposed using 7-valued logic, and applied to the delay fault simulation of self-checking error checkers. The simulated results are compared with those obtained using either a nonrobustly-tested gate-delay fault model or a path-delay fault model. Experiments show that the robustly-tested gate-delay fault model gives the most pessimistic evaluation for delay test effectiveness. The CMOS pass transistor logic implementation of the self-checking error checkers is discussed.<<ETX>>","PeriodicalId":440536,"journal":{"name":"[Proceedings] 1991 International Workshop on Defect and Fault Tolerance on VLSI Systems","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115577871","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Some results and open problems concerning memory reconfiguration under clustered fault models 聚类故障模型下内存重构的一些结果及有待解决的问题
[Proceedings] 1991 International Workshop on Defect and Fault Tolerance on VLSI Systems Pub Date : 1991-11-18 DOI: 10.1109/DFTVS.1991.199972
D. Blough, A. Pelc
{"title":"Some results and open problems concerning memory reconfiguration under clustered fault models","authors":"D. Blough, A. Pelc","doi":"10.1109/DFTVS.1991.199972","DOIUrl":"https://doi.org/10.1109/DFTVS.1991.199972","url":null,"abstract":"Reconfiguration of memory arrays using spare rows and spare columns has been shown to be a useful technique for yield enhancement. This problem is NP-hard in general and hence, previous work has focused on branch-and-bound algorithms for smaller problems and approximation algorithms for larger problems. Recently, the performances of several algorithms have been evaluated under a probabilistic model for memory defects that assumes faults in memory cells occur independently. In this paper, the authors describe some results for the array reconfiguration problem under compound probabilistic models that allow for clustering of faults.<<ETX>>","PeriodicalId":440536,"journal":{"name":"[Proceedings] 1991 International Workshop on Defect and Fault Tolerance on VLSI Systems","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121456614","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Concurrent error diagnosis in mesh array architectures based on overlapping H-processes 基于重叠h进程的网格阵列并发错误诊断
[Proceedings] 1991 International Workshop on Defect and Fault Tolerance on VLSI Systems Pub Date : 1991-11-18 DOI: 10.1109/DFTVS.1991.199955
E. Manolakos, D. Dakhil, M. Vai
{"title":"Concurrent error diagnosis in mesh array architectures based on overlapping H-processes","authors":"E. Manolakos, D. Dakhil, M. Vai","doi":"10.1109/DFTVS.1991.199955","DOIUrl":"https://doi.org/10.1109/DFTVS.1991.199955","url":null,"abstract":"Unlike other methods for concurrent error detection and location (CED), the one proposed is not application specific and does not require fault free comparators and custom VLSI design for the processing cells. It is suitable for any algorithm that can be decomposed in block operations of the format ((a op/sup 1/ b) op/sup 2/ (c op/sup 3/ d)), where a, b, c, d are arbitrary operands and op/sup 1/, op/sup 2/, op/sup 3/ dyadic operators. The process of computing such an operation in a distributed and redundant way on an H-tree shaped sub-array is called an H-process. Many H-processes can overlap providing a general purpose mechanism for run-time fault tolerance in data driven mesh array architectures. Errors can be detected during normal operation. Suspected erroneous results can be masked while location is attempted. There is no need for retries. Diagnosis is achieved 'on the fly' without graceful degradation, upon detection.<<ETX>>","PeriodicalId":440536,"journal":{"name":"[Proceedings] 1991 International Workshop on Defect and Fault Tolerance on VLSI Systems","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117267418","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Wafer-scale massively parallel computing modules for fault-tolerant signal and data processing 用于容错信号和数据处理的晶圆级大规模并行计算模块
[Proceedings] 1991 International Workshop on Defect and Fault Tolerance on VLSI Systems Pub Date : 1991-11-18 DOI: 10.1109/DFTVS.1991.199940
R. Lea
{"title":"Wafer-scale massively parallel computing modules for fault-tolerant signal and data processing","authors":"R. Lea","doi":"10.1109/DFTVS.1991.199940","DOIUrl":"https://doi.org/10.1109/DFTVS.1991.199940","url":null,"abstract":"A WASP device is a WSI implementation of an ASP (Associative String Processor) substring and, as such, it constitutes a fundamental building block for the assembly of SIMD Massively Parallel Computer (MPC) components. This paper describes current progress in the WASP 3/4/5 programme.<<ETX>>","PeriodicalId":440536,"journal":{"name":"[Proceedings] 1991 International Workshop on Defect and Fault Tolerance on VLSI Systems","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125521188","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Applications of a mechanistic yield model for MOSIC chips MOSIC晶片机械良率模型之应用
[Proceedings] 1991 International Workshop on Defect and Fault Tolerance on VLSI Systems Pub Date : 1991-11-18 DOI: 10.1109/DFTVS.1991.199945
C. Drum
{"title":"Applications of a mechanistic yield model for MOSIC chips","authors":"C. Drum","doi":"10.1109/DFTVS.1991.199945","DOIUrl":"https://doi.org/10.1109/DFTVS.1991.199945","url":null,"abstract":"A mechanistic random-defect yield model has been extended to several CMOS technologies and applied to several types of circuit forms. Inputs to the model include critical geometries for yield analysis obtained from detailed layout analysis, and defect density values obtained from large area test structures, with both inputs being needed for each mechanism. A generally applicable yield model metric is proposed to evaluate the effectiveness of any model. Validation of the present model is given in terms of comparisons of model yields (i) with actual yields and (ii) with yield loss per mechanism as determined by physical analysis of non-functional chips. This model is useful in yield improvement work, since it gives a quantitative analysis of yield loss in terms of particular physical mechanisms. The effects of improving an individual processing step can be quantitatively modeled.<<ETX>>","PeriodicalId":440536,"journal":{"name":"[Proceedings] 1991 International Workshop on Defect and Fault Tolerance on VLSI Systems","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128002679","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Circuit-level modeling of spot defects 点状缺陷的电路级建模
[Proceedings] 1991 International Workshop on Defect and Fault Tolerance on VLSI Systems Pub Date : 1991-11-18 DOI: 10.1109/DFTVS.1991.199946
D. Gaitonde, D. Walker
{"title":"Circuit-level modeling of spot defects","authors":"D. Gaitonde, D. Walker","doi":"10.1109/DFTVS.1991.199946","DOIUrl":"https://doi.org/10.1109/DFTVS.1991.199946","url":null,"abstract":"Describes some of the problems faced in mapping spot defects (e.g. extra/missing material, gate oxide pinholes) to changes in the nominal circuit. Traditionally, a very simple mapping has been used, with circuit faults assumed to consist of shorts, opens and occasionally, extra devices. The authors discuss some of the problems in achieving the simple mapping and how they are solved in VLASIC catastrophic fault yield simulator. They also describe modeling problems that appear to require full 3-D device simulation. Finally some investigations into the hazy boundary between parametric and functional faults are described.<<ETX>>","PeriodicalId":440536,"journal":{"name":"[Proceedings] 1991 International Workshop on Defect and Fault Tolerance on VLSI Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116059127","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Hex-repair: a new approach to hexagonal array reconfiguration 六边形修复:一种六边形阵列重构的新方法
[Proceedings] 1991 International Workshop on Defect and Fault Tolerance on VLSI Systems Pub Date : 1991-11-18 DOI: 10.1109/DFTVS.1991.199971
R. Venkateswaran, P. Mazumder, K. Shin
{"title":"Hex-repair: a new approach to hexagonal array reconfiguration","authors":"R. Venkateswaran, P. Mazumder, K. Shin","doi":"10.1109/DFTVS.1991.199971","DOIUrl":"https://doi.org/10.1109/DFTVS.1991.199971","url":null,"abstract":"Presents a new approach to the reconfiguration problem for regular hexagonal arrays that find numerous applications in VLSI and WSI designs such as multipliers, signal processing circuits, etc. Efficient heuristics are used to obtain a fast solution that has excellent fault-coverage characteristics even in the presence of multiple faults.<<ETX>>","PeriodicalId":440536,"journal":{"name":"[Proceedings] 1991 International Workshop on Defect and Fault Tolerance on VLSI Systems","volume":"105 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123412917","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
On the modeling and testing of gate oxide shorts in CMOS logic gates CMOS逻辑门栅氧化短路的建模与测试
[Proceedings] 1991 International Workshop on Defect and Fault Tolerance on VLSI Systems Pub Date : 1991-11-18 DOI: 10.1109/DFTVS.1991.199958
Hong Hao, E. McCluskey
{"title":"On the modeling and testing of gate oxide shorts in CMOS logic gates","authors":"Hong Hao, E. McCluskey","doi":"10.1109/DFTVS.1991.199958","DOIUrl":"https://doi.org/10.1109/DFTVS.1991.199958","url":null,"abstract":"The electrical and logic operation of CMOS simple logic gates in the presence of gate oxide shorts is analyzed using realistic defect models. These models reflect the resistive nature of gate oxide shorts and the difference between n- and p-channel transistors. The resistance of a short plays a central role in determining the actual circuit behavior. Faults caused by gate oxide shorts can be dependent not only on inputs to the gate containing the fault but also on other signals in the circuit, and can escape tests generated using normal TPG schemes. The stuck-at test set for a logic gate cannot guarantee to detect all transistor gate-to-source and gate-to-drain shorts in the logic gate. Gate oxide shorts in n-channel transistors affect circuit operation more severely than those in p-channel transistors do. Some limitations of present transistor-level fault modeling techniques are revealed.<<ETX>>","PeriodicalId":440536,"journal":{"name":"[Proceedings] 1991 International Workshop on Defect and Fault Tolerance on VLSI Systems","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130278493","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 27
A method for the consistent reporting of fault coverage 一种一致报告故障覆盖率的方法
[Proceedings] 1991 International Workshop on Defect and Fault Tolerance on VLSI Systems Pub Date : 1991-11-18 DOI: 10.1109/DFTVS.1991.199964
W. Debany, K.A. Kwait, S. Al-Arian
{"title":"A method for the consistent reporting of fault coverage","authors":"W. Debany, K.A. Kwait, S. Al-Arian","doi":"10.1109/DFTVS.1991.199964","DOIUrl":"https://doi.org/10.1109/DFTVS.1991.199964","url":null,"abstract":"A standard procedure has been developed for fault coverage measurement. Procedure 5012 of MIL-STD-883 governs the reporting of fault coverage for digital microcircuits for military applications. It describes requirements for the development of the logic model for an IC, fault universe, fault simulation, and reporting of results. Procedure 5012 provides a consistent means of measuring fault coverage for an integrated circuit regardless of the specific logic and fault simulator used. It addresses the testing of complex, embedded structures that are not implemented in terms of logic gates, such as RAMs, ROMs, and PLAs. Fault coverages for gate-level and non-gate-level structures are weighted by transistor counts to arrive at an overall fault coverage value. The procedure addresses built-in-self-test based on the use of linear feedback shift registers for output data compaction. Two fault sampling procedures are permitted. A Fault Simulation Report documents the fault coverage level obtained, as well as the assumptions, approximations, and methods used.<<ETX>>","PeriodicalId":440536,"journal":{"name":"[Proceedings] 1991 International Workshop on Defect and Fault Tolerance on VLSI Systems","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126087403","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：481959085
Book学术官方微信