A method for the consistent reporting of fault coverage

[Proceedings] 1991 International Workshop on Defect and Fault Tolerance on VLSI Systems Pub Date : 1991-11-18 DOI:10.1109/DFTVS.1991.199964

W. Debany, K.A. Kwait, S. Al-Arian

{"title":"A method for the consistent reporting of fault coverage","authors":"W. Debany, K.A. Kwait, S. Al-Arian","doi":"10.1109/DFTVS.1991.199964","DOIUrl":null,"url":null,"abstract":"A standard procedure has been developed for fault coverage measurement. Procedure 5012 of MIL-STD-883 governs the reporting of fault coverage for digital microcircuits for military applications. It describes requirements for the development of the logic model for an IC, fault universe, fault simulation, and reporting of results. Procedure 5012 provides a consistent means of measuring fault coverage for an integrated circuit regardless of the specific logic and fault simulator used. It addresses the testing of complex, embedded structures that are not implemented in terms of logic gates, such as RAMs, ROMs, and PLAs. Fault coverages for gate-level and non-gate-level structures are weighted by transistor counts to arrive at an overall fault coverage value. The procedure addresses built-in-self-test based on the use of linear feedback shift registers for output data compaction. Two fault sampling procedures are permitted. A Fault Simulation Report documents the fault coverage level obtained, as well as the assumptions, approximations, and methods used.<<ETX>>","PeriodicalId":440536,"journal":{"name":"[Proceedings] 1991 International Workshop on Defect and Fault Tolerance on VLSI Systems","volume":"40 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1991-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"[Proceedings] 1991 International Workshop on Defect and Fault Tolerance on VLSI Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DFTVS.1991.199964","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 4

Abstract

A standard procedure has been developed for fault coverage measurement. Procedure 5012 of MIL-STD-883 governs the reporting of fault coverage for digital microcircuits for military applications. It describes requirements for the development of the logic model for an IC, fault universe, fault simulation, and reporting of results. Procedure 5012 provides a consistent means of measuring fault coverage for an integrated circuit regardless of the specific logic and fault simulator used. It addresses the testing of complex, embedded structures that are not implemented in terms of logic gates, such as RAMs, ROMs, and PLAs. Fault coverages for gate-level and non-gate-level structures are weighted by transistor counts to arrive at an overall fault coverage value. The procedure addresses built-in-self-test based on the use of linear feedback shift registers for output data compaction. Two fault sampling procedures are permitted. A Fault Simulation Report documents the fault coverage level obtained, as well as the assumptions, approximations, and methods used.<>

查看原文本刊更多论文

一种一致报告故障覆盖率的方法

已经制定了故障覆盖测量的标准程序。MIL-STD-883程序5012规定了军事应用的数字微电路的故障覆盖报告。它描述了开发IC逻辑模型、故障范围、故障模拟和结果报告的需求。程序5012提供了测量集成电路故障覆盖率的一致方法，而不考虑使用的具体逻辑和故障模拟器。它解决了复杂的嵌入式结构的测试，这些结构不是按照逻辑门来实现的，比如ram、rom和pla。栅极级和非栅极级结构的故障覆盖率由晶体管数量加权，从而得到一个总的故障覆盖率值。该程序解决了基于使用线性反馈移位寄存器进行输出数据压缩的内置自检。允许两次故障抽样程序。故障模拟报告记录了所获得的故障覆盖级别，以及所使用的假设、近似和方法。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

求助全文

约1分钟内获得全文求助全文

来源期刊

[Proceedings] 1991 International Workshop on Defect and Fault Tolerance on VLSI Systems

自引率

0.00%

发文量