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[Proceedings] 1991 International Workshop on Defect and Fault Tolerance on VLSI Systems最新文献

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Defect tolerance and yield for a WSI rapid prototyping architecture WSI快速原型架构的缺陷容忍度和良率
[Proceedings] 1991 International Workshop on Defect and Fault Tolerance on VLSI Systems Pub Date : 1991-11-18 DOI: 10.1109/DFTVS.1991.199941
V. Jain, D. Keezer, H. Hikawa
{"title":"Defect tolerance and yield for a WSI rapid prototyping architecture","authors":"V. Jain, D. Keezer, H. Hikawa","doi":"10.1109/DFTVS.1991.199941","DOIUrl":"https://doi.org/10.1109/DFTVS.1991.199941","url":null,"abstract":"Defect tolerance, modeling of harvesting probability, and yield estimation for a WSI rapid prototyping architecture are discussed. Pooled redundancy is utilized to realize reduced reconfiguration complexity while at the same time achieving high harvesting performance. A new harvesting probability model is developed which quickly leads to an estimate of wafer yield. The parameters of the model are chosen by regression upon harvesting data. Using this tool the designer can make tradeoffs between the provisioning of needed functional cells and spares, and the desired yield. The application of this tool is demonstrated upon a rapid prototyping WSI architecture the authors' have developed. Unlike application specific WSI designs reported in the past, their WSI architectural approach involves the mapping of a large class of algorithms with only two types of processing cells. For example, they have mapped a radix-8 FFT algorithm to this wafer architecture. They have also mapped the L-U decomposition algorithm on to this prototyping architecture.<<ETX>>","PeriodicalId":440536,"journal":{"name":"[Proceedings] 1991 International Workshop on Defect and Fault Tolerance on VLSI Systems","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124184234","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
On the testability of realistic bridging faults 现实桥接故障的可测试性研究
[Proceedings] 1991 International Workshop on Defect and Fault Tolerance on VLSI Systems Pub Date : 1991-11-18 DOI: 10.1109/DFTVS.1991.199959
M.B. Santos, J. Sousa, F. Gonçalves, J. P. Teixeira
{"title":"On the testability of realistic bridging faults","authors":"M.B. Santos, J. Sousa, F. Gonçalves, J. P. Teixeira","doi":"10.1109/DFTVS.1991.199959","DOIUrl":"https://doi.org/10.1109/DFTVS.1991.199959","url":null,"abstract":"Discusses the preliminary simulation results concerning the coverage of realistic bridging faults, according to an experimental fault classification of node shorts between logic nodes. There is evidence to support that, prior to simulation, difficult to detect faults can be identified, according to their topological characteristics. This may allow the definition of manageable subsets of bridging faults, whose avoidance by layout reconfiguration may be rewarding.<<ETX>>","PeriodicalId":440536,"journal":{"name":"[Proceedings] 1991 International Workshop on Defect and Fault Tolerance on VLSI Systems","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122783643","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Knowledge-based electrical monitor approach using very large array yield structures to delineate defects during process development and production yield improvement 基于知识的电气监控方法，使用非常大的阵列良率结构来描述工艺开发和生产良率改进过程中的缺陷
[Proceedings] 1991 International Workshop on Defect and Fault Tolerance on VLSI Systems Pub Date : 1991-11-18 DOI: 10.1109/DFTVS.1991.199947
J. Hammond, G. Sery
{"title":"Knowledge-based electrical monitor approach using very large array yield structures to delineate defects during process development and production yield improvement","authors":"J. Hammond, G. Sery","doi":"10.1109/DFTVS.1991.199947","DOIUrl":"https://doi.org/10.1109/DFTVS.1991.199947","url":null,"abstract":"A knowledge-based system has been developed for a set of very large electrical test pattern structures that allows one to understand and debug process problems in sub-micron EPROM/Flash technology. These structures are called 'MONGOS' due to their size ( approximately 300 K Cells) and were designed using the process target EPROM or Flash cells in an array as an exact replica of the product vehicle. Resistance and IV measurements, on pieces of the MONGOs complete with gate and substrate bias control, provide raw data input. The entire 300 K cells can be treated like one giant transistor. A post-processor program creates defect bins from these data for each layer deconfounding the defects according to rules defined in a set of calculation files. The approach is flexible in that defect bins (models) can be defined and implemented as mechanisms are refined; it is also fast since >300 K cells are tested in parallel. Thus, process improvements can be engineered much faster.<<ETX>>","PeriodicalId":440536,"journal":{"name":"[Proceedings] 1991 International Workshop on Defect and Fault Tolerance on VLSI Systems","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129674564","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Optimization of parametric yield 参数产量优化
[Proceedings] 1991 International Workshop on Defect and Fault Tolerance on VLSI Systems Pub Date : 1900-01-01 DOI: 10.1109/DFTVS.1991.199938
S. W. Director
{"title":"Optimization of parametric yield","authors":"S. W. Director","doi":"10.1109/DFTVS.1991.199938","DOIUrl":"https://doi.org/10.1109/DFTVS.1991.199938","url":null,"abstract":"Yield loss can be characterized as either catastrophic or parametric. Catastrophic yield loss is primarily do to local, or spot, defects that occur in a manufacturing process. On the other hand, parametric yield loss is due to global disturbances, such as mask misalignment. In this paper the author explores these two different types of yield loss and then reviews some methods that have been developed to maximize parametric yield.<<ETX>>","PeriodicalId":440536,"journal":{"name":"[Proceedings] 1991 International Workshop on Defect and Fault Tolerance on VLSI Systems","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133988061","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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