Defect tolerance and yield for a WSI rapid prototyping architecture

Abstract

Defect tolerance, modeling of harvesting probability, and yield estimation for a WSI rapid prototyping architecture are discussed. Pooled redundancy is utilized to realize reduced reconfiguration complexity while at the same time achieving high harvesting performance. A new harvesting probability model is developed which quickly leads to an estimate of wafer yield. The parameters of the model are chosen by regression upon harvesting data. Using this tool the designer can make tradeoffs between the provisioning of needed functional cells and spares, and the desired yield. The application of this tool is demonstrated upon a rapid prototyping WSI architecture the authors' have developed. Unlike application specific WSI designs reported in the past, their WSI architectural approach involves the mapping of a large class of algorithms with only two types of processing cells. For example, they have mapped a radix-8 FFT algorithm to this wafer architecture. They have also mapped the L-U decomposition algorithm on to this prototyping architecture.<>