{"title":"基于知识的电气监控方法,使用非常大的阵列良率结构来描述工艺开发和生产良率改进过程中的缺陷","authors":"J. Hammond, G. Sery","doi":"10.1109/DFTVS.1991.199947","DOIUrl":null,"url":null,"abstract":"A knowledge-based system has been developed for a set of very large electrical test pattern structures that allows one to understand and debug process problems in sub-micron EPROM/Flash technology. These structures are called 'MONGOS' due to their size ( approximately 300 K Cells) and were designed using the process target EPROM or Flash cells in an array as an exact replica of the product vehicle. Resistance and IV measurements, on pieces of the MONGOs complete with gate and substrate bias control, provide raw data input. The entire 300 K cells can be treated like one giant transistor. A post-processor program creates defect bins from these data for each layer deconfounding the defects according to rules defined in a set of calculation files. The approach is flexible in that defect bins (models) can be defined and implemented as mechanisms are refined; it is also fast since >300 K cells are tested in parallel. Thus, process improvements can be engineered much faster.<<ETX>>","PeriodicalId":440536,"journal":{"name":"[Proceedings] 1991 International Workshop on Defect and Fault Tolerance on VLSI Systems","volume":"8 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1991-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":"{\"title\":\"Knowledge-based electrical monitor approach using very large array yield structures to delineate defects during process development and production yield improvement\",\"authors\":\"J. Hammond, G. Sery\",\"doi\":\"10.1109/DFTVS.1991.199947\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A knowledge-based system has been developed for a set of very large electrical test pattern structures that allows one to understand and debug process problems in sub-micron EPROM/Flash technology. These structures are called 'MONGOS' due to their size ( approximately 300 K Cells) and were designed using the process target EPROM or Flash cells in an array as an exact replica of the product vehicle. Resistance and IV measurements, on pieces of the MONGOs complete with gate and substrate bias control, provide raw data input. The entire 300 K cells can be treated like one giant transistor. A post-processor program creates defect bins from these data for each layer deconfounding the defects according to rules defined in a set of calculation files. The approach is flexible in that defect bins (models) can be defined and implemented as mechanisms are refined; it is also fast since >300 K cells are tested in parallel. Thus, process improvements can be engineered much faster.<<ETX>>\",\"PeriodicalId\":440536,\"journal\":{\"name\":\"[Proceedings] 1991 International Workshop on Defect and Fault Tolerance on VLSI Systems\",\"volume\":\"8 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1991-11-18\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"9\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"[Proceedings] 1991 International Workshop on Defect and Fault Tolerance on VLSI Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DFTVS.1991.199947\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"[Proceedings] 1991 International Workshop on Defect and Fault Tolerance on VLSI Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DFTVS.1991.199947","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 9
摘要
针对一组非常大的电气测试模式结构,开发了一个基于知识的系统,使人们能够理解和调试亚微米EPROM/Flash技术中的过程问题。由于其尺寸(约300 K Cells),这些结构被称为“MONGOS”,并且是使用阵列中的过程目标EPROM或Flash单元作为产品载体的精确复制品而设计的。电阻和IV测量,在MONGOs上完成栅极和衬底偏置控制,提供原始数据输入。整个300k电池可以当作一个巨大的晶体管来处理。一个后处理程序从这些数据中为每一层创建缺陷箱,根据一组计算文件中定义的规则来分解缺陷。该方法是灵活的,因为缺陷箱(模型)可以随着机制的细化而定义和实现;它也很快,因为> 300k的电池被并行测试。因此,可以更快地设计过程改进。
Knowledge-based electrical monitor approach using very large array yield structures to delineate defects during process development and production yield improvement
A knowledge-based system has been developed for a set of very large electrical test pattern structures that allows one to understand and debug process problems in sub-micron EPROM/Flash technology. These structures are called 'MONGOS' due to their size ( approximately 300 K Cells) and were designed using the process target EPROM or Flash cells in an array as an exact replica of the product vehicle. Resistance and IV measurements, on pieces of the MONGOs complete with gate and substrate bias control, provide raw data input. The entire 300 K cells can be treated like one giant transistor. A post-processor program creates defect bins from these data for each layer deconfounding the defects according to rules defined in a set of calculation files. The approach is flexible in that defect bins (models) can be defined and implemented as mechanisms are refined; it is also fast since >300 K cells are tested in parallel. Thus, process improvements can be engineered much faster.<>