2017 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS)最新文献

{"title":"Low-power multi-sensor system with task scheduling and autonomous standby mode transition control for IoT applications","authors":"M. Hayashikoshi, H. Noda, H. Kawai, K. Nii, H. Kondo","doi":"10.1109/CoolChips.2017.7946385","DOIUrl":"https://doi.org/10.1109/CoolChips.2017.7946385","url":null,"abstract":"The low-power multi-sensor system with task scheduling and autonomous standby mode transition control for IoT applications are proposed, which achieves almost zero standby power at the no-operation modes. A power management scheme with activity localization can reduce the number of transitions between power-on and power-off modes with re-scheduling and bundling task procedures. And autonomously standby mode transition control selects the optimum standby mode of microcontrollers, reducing total power consumption. We demonstrate with evaluation board as a use case of IoT applications, observing 91% power reductions by adopting task scheduling and autonomously standby mode transition control combination.","PeriodicalId":439955,"journal":{"name":"2017 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS)","volume":"314 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122805814","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Intelligence Boosting Engine (IBE): A hardware accelerator for processing sensor fusion and machine learning algorithm for a sensor hub SoC","authors":"Minkwan Kee, Seung-Jin Lee, Hyun-Su Seon, Jongsung Lee, Gi-Ho Park","doi":"10.1109/CoolChips.2017.7946377","DOIUrl":"https://doi.org/10.1109/CoolChips.2017.7946377","url":null,"abstract":"This paper proposes a hardware accelerator, named IBE (Intelligence Boost Engine), to process both sensor fusion and machine learning algorithms for the Standing-egg SLH200 sensor hub SoC. The IBE is designed to have both efficiency and flexibility to support various emerging applications for future sensor hub SoCs in addition to the sensor fusion and machine learning algorithm (SVM) which are the target applications of the SLH200. With regard to the SLH200 SoC, the IBE was fabricated in the Global Foundry 55nm process, and the performance and power evaluation with IBE have been performed with the evaluation board of the SLH200 SoC. The evaluation results show that the proposed IBE can achieve up to 31.3× faster speed for target kernel operation and 4× faster speed for the target application (SVM polynomial). It reduces the energy consumption up to 75% as well.","PeriodicalId":439955,"journal":{"name":"2017 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129824261","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An Adjacent-Line-Merging Writeback Scheme for STT-RAM last-level caches","authors":"Masayuki Sato, Zentaro Sakai, Ryusuke Egawa, Hiroaki Kobayashi","doi":"10.1109/CoolChips.2017.7946380","DOIUrl":"https://doi.org/10.1109/CoolChips.2017.7946380","url":null,"abstract":"Spin-Transfer Torque RAM (STT-RAM) has a higher density than SRAM and non-volatility, and is expected to be used as the last-level cache (LLC) of a microprocessor. One technical issue is that, since the energy cost of write access requests for an STT-RAM LLC is expensive, the total energy consumption of the STT-RAM LLC may increase for some write-intensive applications. Therefore, this paper proposes an Adjacent-Line-Merging Writeback Scheme. The proposed scheme dynamically merges two adjacent lines and write them back to the STT-RAM LLC as one line. The evaluation results show that the proposed scheme can reduce the energy consumption by up to 28%, and 10.4% on average.","PeriodicalId":439955,"journal":{"name":"2017 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS)","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132058855","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Blackghost: An ultra-low-power all-in-one 28nm CMOS SoC for Internet-of-Things","authors":"Y. Pu, G. Samson, Chunlei Shi, Dongkyu Park, K. Easton, R. Beraha, J. Hadi, Mark Lin, E. Arvelo, J. Fatehi, J. Kumar, Moses Derkalousdian, P. Aghera, Adam Newham, H. Sheraji, K. Chatha, R. McLaren, V. Ganesan, S. Namasivayam, D. Butterfield, R. Shenoy, Rashid Attar","doi":"10.1109/CoolChips.2017.7946384","DOIUrl":"https://doi.org/10.1109/CoolChips.2017.7946384","url":null,"abstract":"This paper introduces the Blackghost 1.0, which is a test chip that paved the way for Qualcomm's newest Blackghost ultra-low-power mixed-signal SoC product family. Specifically targeted at battery-powered Internet-of-Things, wearables and e-medical applications, Blackghost delivers unparalleled power efficiency through low-power innovations from software, architecture and circuit design. It integrates a small footprint sensor/control processor based on ARM Cortex M0, an on-die power management unit with direct battery attach capability, a computer vision classifier processor, a programmable DSP hardware accelerator and an ultra-low-power analog front end on a 3 × 3 mm2 die in TSMC 28LP CMOS process technology. The computation operating at near-threshold voltages (<0.6V) is clocked at frequencies up to 50 MHz and draws <9µA/MHz from the directly attached battery.","PeriodicalId":439955,"journal":{"name":"2017 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114494070","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Panel discussions: “Cool chips for the next decade”","authors":"H. Amano, Tadao Nakamura, Hiroaki Kobayashi, H. Kasahara, Y. Hagiwara, J. Burns, D. Brash","doi":"10.1109/CoolChips.2017.7946378","DOIUrl":"https://doi.org/10.1109/CoolChips.2017.7946378","url":null,"abstract":"The advance of CMOS process is still going, but the end is coming into sight. Semiconductor chips with advanced process later than 21nm are so expensive that they are developed only for million selling products. On the other hand, the advanced AI, IoT and big data technologies require more and more computation/communication power with a tightly limited power budget. How we can develop a “Cool chips” in the next decade? And how can the conference “Cool chips” contribute?","PeriodicalId":439955,"journal":{"name":"2017 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124210056","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Message from the organizing committee chair","authors":"Hiroaki Kobayashi","doi":"10.1109/CoolChips.2016.7503663","DOIUrl":"https://doi.org/10.1109/CoolChips.2016.7503663","url":null,"abstract":"It is a pleasure for me to welcome you to the COOL Chips 20, the 20th anniversary of the IEEE Symposium on Low-Power and High-Speed Chips. COOL Chips Conference Series started in 1998, which was held in Tokyo as a one-day event of invited talks only. Now COOL Chips is a three-day event fully sponsored by IEEE Computer Society, which covers not only the chip architecture design, but also software technologies at system software and application levels.","PeriodicalId":439955,"journal":{"name":"2017 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124486816","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"List of the committees members","authors":"","doi":"10.1109/coolchips.2017.7946371","DOIUrl":"https://doi.org/10.1109/coolchips.2017.7946371","url":null,"abstract":"","PeriodicalId":439955,"journal":{"name":"2017 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS)","volume":"566 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132305317","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Front matter","authors":"Felix Naumann","doi":"10.1137/1.9781611974010.fm","DOIUrl":"https://doi.org/10.1137/1.9781611974010.fm","url":null,"abstract":"UNLABELLED\u0000Healthcare delivery systems have been evolving to rely more heavily on technology. There has been a shift in care prevention, diagnosis and treatment which has decreased the importance of traditional methods of care delivery. We have put a great deal of effort into the definition of the structure of the volume and in the sequence of the contributions, so that those in search of a specific reading path will be rewarded. To this end we have divided the different chapters into six main sections: 1. Editorial: This introductory text expresses the position of the Editors - Brenda K. Wiederhold and Giuseppe Riva - about the focus of this year issue; 2. Critical Reviews: These chapters summarize and evaluate emerging cybertherapy topics, including technology-enhanced rehabilitation, Interreality, and Intersubjectivity; 3. Evaluation Studies: These chapters are generally undertaken to solve some specific practical problems and yield decisions about the value of cybertherapy interventions; 4. Original Research: These chapters research studies addressing new cybertherapy methods or approaches; 5.\u0000\u0000\u0000CLINICAL OBSERVATIONS\u0000These chapters include case studies or research protocols with long-term potential. 6. Work in Progress: These chapters include papers describing a future research work. For both health professionals and patients, the selected contents will play an important role in ensuring that the necessary skills and familiarity with the tools are available, as well as a fair understanding of the context of interaction in which they operate. In conclusion, this volume underlines how cybertherapy has started to make progress in treating a variety of disorders. However, there is more work to be done in a number of areas, including the development of easy-to-use and more affordable hardware and software, the development of objective measurement tools, the need to address potential side effects, and the implementation of more controlled studies to evaluate the strength of cybertherapy in comparison to traditional therapies. We are grateful to Chelsie Boyd from the Virtual Reality Medical Institute for her work in collecting and coordinating chapters for this volume. We sincerely hope that you will find this year's volume to be a fascinating and intellectually stimulating read. We continue to believe that together we can change the face of healthcare. Brenda K. Wiederhold Secretary General International Association of CyberPsychology Training, and Rehabilitation (iACToR) Giuseppe Riva President International Association of CyberPsychology Training, and Rehabilitation (iACToR).","PeriodicalId":439955,"journal":{"name":"2017 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS)","volume":"178 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114921373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Cover page","authors":"E. Friar, J. Porter, V. Ashworth","doi":"10.1093/chromsci/bmv233","DOIUrl":"https://doi.org/10.1093/chromsci/bmv233","url":null,"abstract":"","PeriodicalId":439955,"journal":{"name":"2017 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS)","volume":"247 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121883175","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Message from the advisory committee chair","authors":"Tadao Nakamura","doi":"10.1109/CoolChips.2016.7503664","DOIUrl":"https://doi.org/10.1109/CoolChips.2016.7503664","url":null,"abstract":"On behalf of the advisory committee of COOL Chips 20, I extend greetings to each of the conference attendees. This year we celebrate the 20th anniversary of this conference series that is part of the premier conference series on microprocessor architecture and technology and software. Today we have issues in cloud computing, cyber security, IoT, Big Data, and artificial intelligence, especially deep learning developed with very high performance processors, Big Data and corresponding algorisms.","PeriodicalId":439955,"journal":{"name":"2017 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114578306","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}