2017 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS)最新文献

{"title":"Supporting organization","authors":"","doi":"10.1109/coolchips.2018.8373085","DOIUrl":"https://doi.org/10.1109/coolchips.2018.8373085","url":null,"abstract":"","PeriodicalId":439955,"journal":{"name":"2017 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128994612","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Final program","authors":"H. Kubota, Alberto Gianelli, N. Iliev, Shamma Nasrin, M. Graziano, Amit, Ranjan Trivedi","doi":"10.7326/0003-4819-4-8-1065","DOIUrl":"https://doi.org/10.7326/0003-4819-4-8-1065","url":null,"abstract":"A welcome address to open the 2nd annual Workshop on Wireless Motion Capture and Fine-scale Localization as well as an overview for the newly-formed IEEE CRFID Technical Committee on Motion Capture and Localization. A summary of TC-MoCap's mission and future plans are included. These include additional workshops at two more CRFID-sponsored conferences later this year (IEEE RFID-TA and IEEE WiSEE) as well as a special issue call for papers for IEEE Journal on RFID in the area of Motion Capture and Localization. This talk provides an overview of cellphone location technologies in E911 services today. We'll review location accuracy requirements set by FCC and present technologies currently available to enhance location accuracy further, especially in the vertical dimension, also known as the z-axis. RFID our average mean for a and when and moving. We multi-user an average mean of system for locating In this paper, new compressive sensing (CS)-based direction of arrival (DOA) estimation technique using the beamspace (BS) processing is proposed. Two techniques have been proposed, namely, full beam-space (FBS) as well as multiple beam-space (MBS), and investigated versus the ordinary element-space (ES) technique in a CS-based framework. More, the rank one update covariance matrix has been combined along with all the investigated techniques. Both of the proposed schemes can identify more source signals than the number of sensors used, without requiring an a priori knowledge of the number of source signals to be estimated. The performance of the proposed schemes is compared to that of the ES-based technique. This paper presents a RFID-based mobile robot able of self-locating within an indoor scenario and to estimate the position of target UHF-RFID tags. To locate itself, the robot exploits a sensor-fusion method which combines data from an infrastructure of passive reference RFID tags arranged in known locations and data from rotary wheel encoders. Besides, during its motion it is able of measuring the target tag locations through a synthetic-array approach. The knowledge of the reader antenna trajectory is here achieved from the RFID-based sensor-fusion method which exhibits a localization error lower than 0.27 m for 20-m long paths in a real office environment. Then, the estimated trajectory is exploited for target tag localization with high accuracy by using the synthetic-array approach. This work revisits particle filtering RFID localization methods, solely based on phase measurements. The reader is installed on a low-cost robotic platform, which performs autonomously (and independently from the RFID reader) open source simultaneous localization and mapping (SLAM). In contrast to prior art, the proposed methods introduce a weight metric for each particle-measurement pair, based on geometry arguments, robust to phase measurement noise (e.g., due to multipath). In addition, the methods include the unknown constant phase offset as a parameter to be esti","PeriodicalId":439955,"journal":{"name":"2017 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS)","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121391861","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Keynote & invited speaker's biography","authors":"H. Fu, Haruyoshi Kumura, D. Brash, Nigel Stephens","doi":"10.1109/coolchips.2016.7503669","DOIUrl":"https://doi.org/10.1109/coolchips.2016.7503669","url":null,"abstract":"","PeriodicalId":439955,"journal":{"name":"2017 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124373474","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Special session speaker's biography","authors":"Yutaka Nakamura","doi":"10.1109/coolchips.2016.7503668","DOIUrl":"https://doi.org/10.1109/coolchips.2016.7503668","url":null,"abstract":"","PeriodicalId":439955,"journal":{"name":"2017 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS)","volume":"190 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132783928","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Leveraging asymmetric body bias control for low power LSI design","authors":"Hayate Okuhara, Akram Ben Ahmed, Johannes Maximilian Kühn, H. Amano","doi":"10.1109/CoolChips.2017.7946379","DOIUrl":"https://doi.org/10.1109/CoolChips.2017.7946379","url":null,"abstract":"Asymmetric body bias control technique is proposed and evaluated. Compared to the conventional symmetric body bias control, the proposed technique provides finer performance control. Real chip measurements proved the feasibility of leakage reduction when asymmetric body bias is employed. In our measurement, 22.3% of leakage reduction is achieved when compared to the conventional body bias control. Our work also considers the practical on-chip body bias generator and proposed a technique which can be available with the body bias generator.","PeriodicalId":439955,"journal":{"name":"2017 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130842283","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 216 GOPS flexible WDR Image Processor for ADAS SoC","authors":"Mihir Mody, Hetul Sanghvi, Niraj Nandan, Shashank Dabral, Rajasekhar Allu, R. Sagar, Kedar Chitnis, Jason Jones, Brijesh Jadhav, Sujith Shivalingappa, Aish Dubey","doi":"10.1109/CoolChips.2017.7946383","DOIUrl":"https://doi.org/10.1109/CoolChips.2017.7946383","url":null,"abstract":"Advanced Driver Assistance Systems (ADAS) enhance the ability of a vehicle driver to avoid possible road accidents resulting in a safer driving experience. Front camera ADAS is probably the most challenging of all. These systems require high computational processing, in the range of hundreds of GOPS, within a 4 Watt power budget driven by thermal constraints of small enclosed assembly of the final system. In this paper, we present, Wide Dynamic Image (WDR or HDR) Processor as part of the Imaging Sub-system (ISS) that is flexible to interface with various kinds of optical sensor across different manufactures. The design achieves an overall throughput of 216 GOPS with performance efficiency of 66.4 GOPS/mm2 and power efficiently of 1.8 TOPS/W.","PeriodicalId":439955,"journal":{"name":"2017 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS)","volume":"310 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114399221","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 120 fps high frame rate real-time HEVC video encoder with parallel configuration scalable to 4K","authors":"Yuya Omori, Takayuki Onishi, Hiroe Iwasaki, A. Shimizu","doi":"10.1109/CoolChips.2017.7946382","DOIUrl":"https://doi.org/10.1109/CoolChips.2017.7946382","url":null,"abstract":"This paper describes a new 120 fps (frames per second) real-time HEVC encoder for higher frame rate video encoding and transmission. Modification in the flexible customizable software architecture of encoder LSIs makes it possible to achieve the temporally scalable HEVC encoding with upward compatibility for existing 60 fps-based systems. The encoder also achieves 4K/120fps video encoding in real time through the synchronized operation of multiple 2K/120fps encoders working in parallel. The proposed encoder systems will open the door to the next generation high frame rate UHDTV services.","PeriodicalId":439955,"journal":{"name":"2017 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116467891","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"SPARC64TM XII: Fujitsu's latest 12 core processor for mission critical servers","authors":"T. Maruyama","doi":"10.1109/CoolChips.2017.7946375","DOIUrl":"https://doi.org/10.1109/CoolChips.2017.7946375","url":null,"abstract":"This paper describes the design, microarchitecture, and performance of the latest Fujitsu SPARC64 XII 12 core microprocessor which has been developed for high performance, mission critical servers. Dual instruction pipelines, 8-way SMT (Simultaneous Multi-Threading), a high CPU frequency of over 4 GHz, and a 12 core design have doubled the chip performance compared with the previous SPARC64 X+, while keeping its high single thread performance.","PeriodicalId":439955,"journal":{"name":"2017 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128060905","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An application-adaptive data allocation method for multi-channel memory","authors":"Takuya Toyoshima, Masayuki Sato, Ryusuke Egawa, Hiroaki Kobayashi","doi":"10.1109/CoolChips.2017.7946381","DOIUrl":"https://doi.org/10.1109/CoolChips.2017.7946381","url":null,"abstract":"Modern memory systems are equipped with multiple channels to achieve a higher memory bandwidth. Since the multi-channel memory system focuses on achieving a high memory bandwidth, data are allocated to all the channels. Hence, when the memory system is accessed, all the channels are activated until the next DRAM refresh starts. Therefore, when executing compute-intensive applications that do not need a full memory bandwidth, the memory modules just waste power because of an unnecessary activation. To overcome this problem, this paper proposes a data allocation method, which controls the number of accessed channels for reducing energy consumption according to applications' demands for the memory bandwidth. The evaluation results show that the proposed method reduces the energy consumption by up to 10.4%, and 5.3% on average without degrading the performances.","PeriodicalId":439955,"journal":{"name":"2017 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS)","volume":"667 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131857533","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An energy-efficient deep learning processor with heterogeneous multi-core architecture for convolutional neural networks and recurrent neural networks","authors":"Dongjoo Shin, Jinmook Lee, Jinsu Lee, Juhyoung Lee, H. Yoo","doi":"10.1109/CoolChips.2017.7946376","DOIUrl":"https://doi.org/10.1109/CoolChips.2017.7946376","url":null,"abstract":"An energy-efficient deep learning processor is proposed for convolutional neural networks (CNNs) and recurrent neural networks (RNNs) in mobile platforms. The 16mm2 chip is fabricated using 65nm technology with 3 key features, 1) Reconfigurable heterogeneous architecture to support both CNNs and RNNs, 2) LUT-based reconfigurable multiplier optimized for dynamic fixed-point with the on-line adaptation, 3) Quantization table-based matrix multiplication to reduce off-chip memory access and remove duplicated multiplications. As a result, compared to the [2] and [3], this work shows 20× and 4.5× higher energy efficiency, respectively. Also, DNPU shows 6.5× higher energy efficiency compared to the [5].","PeriodicalId":439955,"journal":{"name":"2017 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131114438","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}