{"title":"SPARC64TM XII:富士通最新的用于关键任务服务器的12核处理器","authors":"T. Maruyama","doi":"10.1109/CoolChips.2017.7946375","DOIUrl":null,"url":null,"abstract":"This paper describes the design, microarchitecture, and performance of the latest Fujitsu SPARC64 XII 12 core microprocessor which has been developed for high performance, mission critical servers. Dual instruction pipelines, 8-way SMT (Simultaneous Multi-Threading), a high CPU frequency of over 4 GHz, and a 12 core design have doubled the chip performance compared with the previous SPARC64 X+, while keeping its high single thread performance.","PeriodicalId":439955,"journal":{"name":"2017 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"SPARC64TM XII: Fujitsu's latest 12 core processor for mission critical servers\",\"authors\":\"T. Maruyama\",\"doi\":\"10.1109/CoolChips.2017.7946375\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper describes the design, microarchitecture, and performance of the latest Fujitsu SPARC64 XII 12 core microprocessor which has been developed for high performance, mission critical servers. Dual instruction pipelines, 8-way SMT (Simultaneous Multi-Threading), a high CPU frequency of over 4 GHz, and a 12 core design have doubled the chip performance compared with the previous SPARC64 X+, while keeping its high single thread performance.\",\"PeriodicalId\":439955,\"journal\":{\"name\":\"2017 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS)\",\"volume\":\"13 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-04-19\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CoolChips.2017.7946375\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CoolChips.2017.7946375","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
摘要
本文介绍了富士通最新的SPARC64 XII 12核微处理器的设计、微架构和性能,该微处理器是为高性能、关键任务服务器开发的。双指令管道、8路SMT (Simultaneous Multi-Threading)、4 GHz以上的高CPU主频和12核设计,使芯片性能比之前的SPARC64 X+提高了一倍,同时保持了较高的单线程性能。
This paper describes the design, microarchitecture, and performance of the latest Fujitsu SPARC64 XII 12 core microprocessor which has been developed for high performance, mission critical servers. Dual instruction pipelines, 8-way SMT (Simultaneous Multi-Threading), a high CPU frequency of over 4 GHz, and a 12 core design have doubled the chip performance compared with the previous SPARC64 X+, while keeping its high single thread performance.