An Adjacent-Line-Merging Writeback Scheme for STT-RAM last-level caches

Abstract

Spin-Transfer Torque RAM (STT-RAM) has a higher density than SRAM and non-volatility, and is expected to be used as the last-level cache (LLC) of a microprocessor. One technical issue is that, since the energy cost of write access requests for an STT-RAM LLC is expensive, the total energy consumption of the STT-RAM LLC may increase for some write-intensive applications. Therefore, this paper proposes an Adjacent-Line-Merging Writeback Scheme. The proposed scheme dynamically merges two adjacent lines and write them back to the STT-RAM LLC as one line. The evaluation results show that the proposed scheme can reduce the energy consumption by up to 28%, and 10.4% on average.