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2017 IEEE Asian Solid-State Circuits Conference (A-SSCC)最新文献

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A 130nm 1Mb HfOx embedded RRAM macro using self-adaptive peripheral circuit system techniques for 1.6X work temperature range 采用自适应外围电路系统技术的130nm 1Mb HfOx嵌入式RRAM宏，工作温度范围为1.6X
2017 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2017-11-01 DOI: 10.1109/ASSCC.2017.8240244
Feng Zhang, Dongyu Fan, Yuan Duan, Jin Li, Cong Fang, Yun Li, Xiaowei Han, Lan Dai, Chengying Chen, J. Bi, Ming Liu, Meng-Fan Chang
{"title":"A 130nm 1Mb HfOx embedded RRAM macro using self-adaptive peripheral circuit system techniques for 1.6X work temperature range","authors":"Feng Zhang, Dongyu Fan, Yuan Duan, Jin Li, Cong Fang, Yun Li, Xiaowei Han, Lan Dai, Chengying Chen, J. Bi, Ming Liu, Meng-Fan Chang","doi":"10.1109/ASSCC.2017.8240244","DOIUrl":"https://doi.org/10.1109/ASSCC.2017.8240244","url":null,"abstract":"This paper designed a 1-Mb HfOx-based embedded Resistive Random Access Memory (RRAM) device with a one-transistor-one-resistor (1T1R) structure, and systematically investigated its working temperature range. It noted that this embedded RRAM macro has a 1.6X working temperature range than previous design for some extreme environment. Using the peripheral-assisted technique, it can enable the error rate of the RRAM macro under 0.5% which can reduce the complexity of ECC function. Experimental results show that, the RRAM macro achieves a wider work temperature range (between −55°C and 150°C), which improves the reliability of the entire embedded RRAM macro and has a high robustness as well.","PeriodicalId":438242,"journal":{"name":"2017 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129086851","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A CMOS time of flight (TOF) depth image sensor with in-pixel background cancellation and sensitivity improvement using phase shifting readout technique 一种采用相移读出技术的CMOS飞行时间(TOF)深度图像传感器，具有像素内背景抵消和灵敏度提高
2017 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2017-11-01 DOI: 10.1109/ASSCC.2017.8240234
Ting Liao, Nien-An Lee, C. Hsieh
{"title":"A CMOS time of flight (TOF) depth image sensor with in-pixel background cancellation and sensitivity improvement using phase shifting readout technique","authors":"Ting Liao, Nien-An Lee, C. Hsieh","doi":"10.1109/ASSCC.2017.8240234","DOIUrl":"https://doi.org/10.1109/ASSCC.2017.8240234","url":null,"abstract":"This paper presents a CMOS time-of-flight (TOF) image sensor with in-pixel background light cancellation for outdoor depth imaging application. The using of P+/N_well diode with proposed polarity switching integration and phase-shift readout (PSR) technique achieves the in-pixel background cancellation capability and sensitivity improvement. Moreover, the PSR also suppresses the column fixed-pattern-noise (FPN) without need of extra frame capturing. A prototype TOF sensing chip with a 64×64 array has been fabricated in TSMC standard 0.18pm CMOS process and verified. The pixel pitch is 20pmx20pm with a fill-factor of 33%. The achieved depth measurement range is 0.75 to 7.5 meters with a linearity error below 1.1%. The measured relative precision is 4.2% at a 7.5-meter target distance; and the background light suppression capability is up to 180k lux without saturation.","PeriodicalId":438242,"journal":{"name":"2017 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128772383","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
On-chip spur and phase noise cancellation techniques 片上杂散和相位噪声消除技术
2017 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2017-11-01 DOI: 10.1109/ASSCC.2017.8240228
Yi-An Li, M. Mar, B. Nikolić, A. Niknejad
{"title":"On-chip spur and phase noise cancellation techniques","authors":"Yi-An Li, M. Mar, B. Nikolić, A. Niknejad","doi":"10.1109/ASSCC.2017.8240228","DOIUrl":"https://doi.org/10.1109/ASSCC.2017.8240228","url":null,"abstract":"Two techniques for spur and phase noise cancellation have been proposed. A fully integrated design achieves a measured spur cancellation of 15dB at 250MHz and 750MHz offset as well as phase noise cancellation from 4MHz to 200MHz offset with maximum 25dB cancellation depth for a 1-GHz clock. The proposed ideas have been verified through a fabricated 65nm CMOS prototype with power consumption of 11mW from a supply voltage of 1.2V.","PeriodicalId":438242,"journal":{"name":"2017 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116274770","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 2.79-mW 0.5%-THD CMOS current driver IC for portable electrical impedance tomography system 用于便携式电阻抗断层成像系统的2.79 mw 0.5% thd CMOS电流驱动IC
2017 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2017-11-01 DOI: 10.1109/ASSCC.2017.8240237
Jaeeun Jang, Minseo Kim, Joonsung Bae, H. Yoo
{"title":"A 2.79-mW 0.5%-THD CMOS current driver IC for portable electrical impedance tomography system","authors":"Jaeeun Jang, Minseo Kim, Joonsung Bae, H. Yoo","doi":"10.1109/ASSCC.2017.8240237","DOIUrl":"https://doi.org/10.1109/ASSCC.2017.8240237","url":null,"abstract":"A low-power and high-accuracy current driver IC is proposed for portable electrical impedance tomography (EIT) systems. The proposed IC supports active electrode configuration and has three key features. First, high output impedance current driver is implemented with phase compensation scheme through a delay-locked loop (DLL) to significantly alleviate a phase shift and a required power consumption in the driver. Second, low-power pseudo-sine wave generator is used not only for a low-harmonic distortion but also for a flexible injection frequency utilization. Through the proposed quantization scheme, total harmonic distortion (THD) is reduced by 35%, achieving THD less than 0.5%. Third, the calibration unit is proposed to compensate injection-current amplitude variations among active electrodes. As a result, the proposed current driver IC guarantees more than 1MΩ output impedance over a wide range of injection current up to 400pA and operating frequency from 1kHz to 5MHz, only consuming 2.79mW.","PeriodicalId":438242,"journal":{"name":"2017 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124411612","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A 67 GHz dual injection quadrature VCO with −182.9 dBc/Hz FOM in 90-nm CMOS 采用- 182.9 dBc/Hz FOM的67 GHz双注入正交压控振荡器
2017 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2017-11-01 DOI: 10.1109/ASSCC.2017.8240226
Cuei-Ling Hsieh, Hong-Shen Chen, Hou-Ru Pan, J. Liu
{"title":"A 67 GHz dual injection quadrature VCO with −182.9 dBc/Hz FOM in 90-nm CMOS","authors":"Cuei-Ling Hsieh, Hong-Shen Chen, Hou-Ru Pan, J. Liu","doi":"10.1109/ASSCC.2017.8240226","DOIUrl":"https://doi.org/10.1109/ASSCC.2017.8240226","url":null,"abstract":"An ultra low phase noise millimeter-wave (mm-wave) quadrature voltage-controlled oscillator (QVCO) is proposed. By introducing an additional coupling path and using uneven sized cross-coupled oscillators with a fully symmetrical layout, the phase noise and the amplitude/phase mismatches are minimized. Implemented in 90-nm CMOS process, the 67-GHz compact QVCO achieves 0.46 degree and 0.47 dB phase and amplitude mismatches, respectively, and a phase noise of −105.8 dBc/Hz at 1-MHz offset, resulting in a figure-of-merit of −183 dBc/Hz.","PeriodicalId":438242,"journal":{"name":"2017 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126952775","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
An 88% efficiency MPPT for PV energy harvesting system with novel switch width modulation for output power 100nW to 0.3mW 在输出功率100nW至0.3mW时，采用新型开关宽度调制的光伏能量收集系统的88%效率MPPT
2017 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2017-11-01 DOI: 10.1109/ASSCC.2017.8240230
Karim Rawy, Taegeun Yoo, T. T. Kim
{"title":"An 88% efficiency MPPT for PV energy harvesting system with novel switch width modulation for output power 100nW to 0.3mW","authors":"Karim Rawy, Taegeun Yoo, T. T. Kim","doi":"10.1109/ASSCC.2017.8240230","DOIUrl":"https://doi.org/10.1109/ASSCC.2017.8240230","url":null,"abstract":"This paper presents a novel three-dimensional maximum power point tracking (3D-MPPT) system for ultra-low power (ULP) solar energy harvesting systems (EHS) for internet of things (IoT) smart nodes. The proposed 3D-MPPT utilizes a gate-source voltage (Vgs) dependent switch width modulation (SWM) technique for improving power efficiency (PE) at standby (<1 μA) and heavy (>300μA) load scenarios, and eliminating the gate driver and conduction loss trade-off for a reconfigurable switched capacitor charge pump (SCCP). The proposed SWM technique modulates the SC transistors size in proportion to the load condition, input voltage and Vgs applied. The tested chip, fabricated in 65-nm CMOS technology, can harvest from 0.35 V and provides a regulated output voltage at 1 V with peak efficiency of 88% at 200 μW and PE > 60% at 100 nW.","PeriodicalId":438242,"journal":{"name":"2017 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132767061","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 82 mW 28 Gb/s PAM-4 digital sequence decoder with built-in error correction in 28nm FDSOI 28nm FDSOI内置纠错功能的82mw 28gb /s PAM-4数字序列解码器
2017 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2017-11-01 DOI: 10.1109/ASSCC.2017.8240222
Masum Hossain, Aurangozeb, A. D. Hossain, Maruf Mohammad
{"title":"A 82 mW 28 Gb/s PAM-4 digital sequence decoder with built-in error correction in 28nm FDSOI","authors":"Masum Hossain, Aurangozeb, A. D. Hossain, Maruf Mohammad","doi":"10.1109/ASSCC.2017.8240222","DOIUrl":"https://doi.org/10.1109/ASSCC.2017.8240222","url":null,"abstract":"This paper describes an energy-efficient PAM-4 digital receiver based on sequence detection. This scheme takes advantage of the ISI in the channel to reconstruct the time domain 5-bit sequence including MSB and LSB. The architecture also enables built-in error correction with very low latency. This concept is demonstrated with prototype implemented in a 28nm FDSOI CMOS using only 18-data comparators. Consuming only 82mW at 28 Gb/s, the receiver is capable of compensating 27 dB channel loss with BER lower than 10−8. With error correction, the receiver can achieve BER lower than 10−10.","PeriodicalId":438242,"journal":{"name":"2017 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"137 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124211362","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 13-bit 160MS/s pipelined subranging-SAR ADC with low-offset dynamic comparator 一个带低偏移动态比较器的13位160MS/s流水线子变换sar ADC
2017 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2017-11-01 DOI: 10.1109/ASSCC.2017.8240257
Weitao Li, Fule Li, Jia Liu, Hongyu Li, Zhihua Wang
{"title":"A 13-bit 160MS/s pipelined subranging-SAR ADC with low-offset dynamic comparator","authors":"Weitao Li, Fule Li, Jia Liu, Hongyu Li, Zhihua Wang","doi":"10.1109/ASSCC.2017.8240257","DOIUrl":"https://doi.org/10.1109/ASSCC.2017.8240257","url":null,"abstract":"A 13-bit 160MS/s hybrid ADC in 65 nm CMOS is presented in this paper. By combining the pipelined, flash and SAR architectures, a hybrid ADC architecture is proposed to improve the power efficiency. An input offset storage technique of dynamic comparator is proposed to increase the conversion linearity. A reference voltage buffer with the charge compensation is proposed to save power and reduce the decoupling capacitor. The achieved peak SNDR, SFDR, and FoM are 64.2 dB, 80.5 dBc, and 107.3 fJ/conversion-step, respectively.","PeriodicalId":438242,"journal":{"name":"2017 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"214 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122845233","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A 0.37mm2 LTE/Wi-Fi compatible, memory-based, runtime-reconfigurable 2n3m5k FFT accelerator integrated with a RISC-V core in 16nm FinFET 一个0.37mm2 LTE/Wi-Fi兼容、基于内存、运行时可重构的2n3m5k FFT加速器，集成了16nm FinFET的RISC-V核心
2017 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2017-11-01 DOI: 10.1109/ASSCC.2017.8240277
Angie Wang, B. Richards, Palmer Dabbelt, Howard Mao, Stevo Bailey, Jaeduk Han, Eric Chang, James Dunn, E. Alon, B. Nikolić
{"title":"A 0.37mm2 LTE/Wi-Fi compatible, memory-based, runtime-reconfigurable 2n3m5k FFT accelerator integrated with a RISC-V core in 16nm FinFET","authors":"Angie Wang, B. Richards, Palmer Dabbelt, Howard Mao, Stevo Bailey, Jaeduk Han, Eric Chang, James Dunn, E. Alon, B. Nikolić","doi":"10.1109/ASSCC.2017.8240277","DOIUrl":"https://doi.org/10.1109/ASSCC.2017.8240277","url":null,"abstract":"Dedicated hardware accelerators enable energy-efficient implementations of radio and imaging basebands. Multistandard, multi-mode radio basebands require an on-the-fly reconfigurable fast Fourier transform (FFT) accelerator that implements many different FFT sizes. An instance of a runtime-reconfigurable 2n3m5k FFT accelerator was generated by a custom hardware generator to meet the requirements of common wireless standards (Wi-Fi, LTE). The accelerator is integrated with a RISC-V processor, and the measured 16nm FinFET chip runs up to 940MHz and consumes 0.46 to 22.6mW of power when running FFT benchmarks for Wi-Fi and LTE symbol lengths.","PeriodicalId":438242,"journal":{"name":"2017 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125170176","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A dual-axis MEMS vibratory gyroscope ASIC with 0.0061°/s/VHz noise floor over 480 Hz bandwidth 双轴MEMS振动陀螺仪ASIC具有0.0061°/s/VHz噪声底限，带宽超过480 Hz
2017 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2017-11-01 DOI: 10.1109/ASSCC.2017.8240206
Z. Tan, K. Nguyen, Jeff Yan, H. Samuels, Shane Keating, Paul Crocker, Bill Clark
{"title":"A dual-axis MEMS vibratory gyroscope ASIC with 0.0061°/s/VHz noise floor over 480 Hz bandwidth","authors":"Z. Tan, K. Nguyen, Jeff Yan, H. Samuels, Shane Keating, Paul Crocker, Bill Clark","doi":"10.1109/ASSCC.2017.8240206","DOIUrl":"https://doi.org/10.1109/ASSCC.2017.8240206","url":null,"abstract":"This paper presents a high performance dual-axis (pitch and roll) MEMS vibratory gyroscope readout ASIC which converts angular rate information to digital output. Two signal processing chains surrounding the MEMS sensor are implemented, namely the drive channel and the sense channel. The drive channel drives the sensor to resonate at its resonant frequency, which produces a velocity of the sensor disc to generate the Coriolis force during angular rotation. The sense channel employs a low noise trans-impedance amplifier (TIA) followed by a demodulator which down-converts the angular rate input signal from the resonant frequency to baseband. Two switched-capacitor (SC) 2-1 MASH delta-sigma ADCs convert the input angular rate from the pitch and roll arises to digital output. The reference of the ADC is also demodulated from the sensor output to cancel out supply voltage dependence. The whole ASIC including the high-voltage MEMS sensor driver, digital-filter, on-chip regulator and temperature sensor is fabricated in a 0.18pm CMOS technology with an area of 7.3 mm2. The design achieves a noise floor of 0.0032°/s/VHz and 0.0061°/s/VHz in full-scale input ranges of 500°/s and 2000°/s, respectively, over a 480Hz signal bandwidth. The bias instability is measured as 2.5°/h at input range of 500°/s. The whole ASIC consumes 7mA from a 3V supply.","PeriodicalId":438242,"journal":{"name":"2017 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"275 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133732822","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
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