2017 IEEE Asian Solid-State Circuits Conference (A-SSCC)最新文献_第4页

An ultra-low phase noise all-digital multi-frequency generator using injection-locked DCOs and time-interleaved calibration 超低相位噪声全数字多频发生器，采用注入锁相dco和时间交错校准

2017 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2017-11-01 DOI: 10.1109/ASSCC.2017.8240283

Suneui Park, Heein Yoon, Jaehyouk Choi

引用次数: 1

Fully-integrated AMLED micro display system with a hybrid voltage regulator 完全集成的AMLED微显示系统与混合电压调节器

2017 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2017-11-01 DOI: 10.1109/ASSCC.2017.8240270

Junmin Jiang, Liusheng Sun, Xu Zhang, S. Yuen, Xianbo Li, W. Ki, C. Yue, K. Lau

引用次数: 8

A fully-synthesizable C-element based PUF featuring temperature variation compensation with native 2.8% BER, 1.02fJ/b at 0.8–1.0V in 40nm 一种完全合成的基于c元素的PUF，具有温度变化补偿功能，原生BER为2.8%，在0.8-1.0V, 40nm下为1.02fJ/b

2017 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2017-11-01 DOI: 10.1109/ASSCC.2017.8240276

Sachin Taneja, A. Alvarez, Gopalakrishnan Sadagopan, M. Alioto

{"title":"A fully-synthesizable C-element based PUF featuring temperature variation compensation with native 2.8% BER, 1.02fJ/b at 0.8–1.0V in 40nm","authors":"Sachin Taneja, A. Alvarez, Gopalakrishnan Sadagopan, M. Alioto","doi":"10.1109/ASSCC.2017.8240276","DOIUrl":"https://doi.org/10.1109/ASSCC.2017.8240276","url":null,"abstract":"A fully-synthesizable Physically Unclonable Function (PUF) with hysteresis-enhanced stability and active compensation of temperature variations is proposed. In detail, a bitcell based on low-voltage regulated Cascode current mirror is introduced. To reduce undesired bit flips, hysteretic behavior is obtained through the insertion of a Muller C-element output stage, which mitigates the effect of noise, voltage and temperature fluctuations on the PUF output. Measurements in a 40nm test chip show that hysteresis improves the bit error rate (BER) by 14%. A feedback scheme is also introduced to compensate the effect of temperature variations at run time, improving the intra-PUF Hamming distance by 40% and BER by 6–7% under temperature variations (25–85°C). Native worst-case BER of 2.8% is measured under 0.8–1.0V and 25–85°C, with instability degradation with temperature being 0.15% per 10°C. The PUF bitcell consumes 1.02fJ/b at 0.9V, achieving an energy efficiency of 16Tbps/W and maximum throughput of 24Gbps. Also, the proposed PUF can be designed with fully automated standard cell-based flows, thus enabling substantial design effort reduction compared to prior art based on custom design styles.","PeriodicalId":438242,"journal":{"name":"2017 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126422038","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

MLC/3LC NAND flash SSD cache with asymmetric error reduction huffman coding for tiered hierarchical storage 采用非对称哈夫曼编码的MLC/3LC NAND闪存SSD缓存

2017 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2017-11-01 DOI: 10.1109/ASSCC.2017.8240240

Hikaru Watanabe, Yoshiaki Deguchi, K. Takeuchi

引用次数: 5

Chaos, deterministic non-periodic flow, for chip-package-board interactive PUF 混沌，确定性非周期流，用于芯片封装板交互PUF

2017 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2017-11-01 DOI: 10.1109/ASSCC.2017.8240207

N. Miura, Masanori Takahashi, K. Nagatomo, M. Nagata

引用次数: 4

NBTI/PBTI separated BTI monitor with 4.2x sensitivity by standard cell based unbalanced ring oscillator NBTI/PBTI分离式BTI监测仪采用基于标准单元的不平衡环形振荡器，灵敏度为4.2倍

2017 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2017-11-01 DOI: 10.1109/ASSCC.2017.8240251

M. Igarashi, Y. Takazawa, Y. Tsukamoto, K. Takeuchi, K. Shibutani

{"title":"NBTI/PBTI separated BTI monitor with 4.2x sensitivity by standard cell based unbalanced ring oscillator","authors":"M. Igarashi, Y. Takazawa, Y. Tsukamoto, K. Takeuchi, K. Shibutani","doi":"10.1109/ASSCC.2017.8240251","DOIUrl":"https://doi.org/10.1109/ASSCC.2017.8240251","url":null,"abstract":"We propose an on-chip bias temperature instabilities (BTI) monitor by using standard cell based unbalanced ring-oscillator (RO). The monitor consists of NAND and NOR with extremely large difference in drive strength, which enables 4.2x sensitivity to BTI compared with normal INV based RO. This originates not only from accentuation of the degraded stage with small drive strength by the dominant delay but also from ΔVth sensitivity improvement of stacked transistors with increasing output transition time. In addition, our proposal allows to monitor either one of negative BTI (NBTI) or positive BTI (PBTI) selectively by making use of the Miller effect caused by the size combination of NOR and NAND. A test chip is implemented in a 28 nm High-k Metal-Gate (HKMG) CMOS technology. We successfully observed that measured results of each RO were well matched with simulations. Owing to this high sensitivity and successful NBTI/PBTI separation, we can detect variations and outliers of BTI at time of testing, and optimize guard band (GB) while considering NBTI/PBTI sensitivity difference of each circuit.","PeriodicalId":438242,"journal":{"name":"2017 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117044427","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

A 15-μW, 103-fs step, 5-bit capacitor-DAC-based constant-slope digital-to-time converter in 28nm CMOS 一种15 μ w、103-fs步进、5位电容- dac的28nm CMOS等斜率数字-时间转换器

2017 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2017-11-01 DOI: 10.1109/ASSCC.2017.8240224

Peng Chen, Feifei Zhang, Zhirui Zong, Hao Zheng, T. Siriburanon, R. Staszewski

引用次数: 8

A 762-pW 16.3-ps resolution digital pulse width modulator using zooming phase-interpolator 采用变焦相位插值器的762-pW 16.3 ps分辨率数字脉宽调制器

2017 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2017-11-01 DOI: 10.1109/ASSCC.2017.8240269

Masanobu Tsuji

引用次数: 2

A 0.5V BJT-based CMOS thermal sensor in 10-nm FinFET technology 基于10nm FinFET技术的0.5V bjt CMOS热传感器

2017 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2017-11-01 DOI: 10.1109/ASSCC.2017.8240211

D. Lin, Hao-Ping Hong

引用次数: 12

A 12.1mW, 60dB SNR, 8-channel beamforming embedded SAR ADC for ultrasound imaging systems 用于超声成像系统的12.1mW, 60dB信噪比，8通道波束形成嵌入式SAR ADC

2017 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2017-11-01 DOI: 10.1109/ASSCC.2017.8240236

Taehoon Kim, Suhwan Kim

引用次数: 8