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2017 IEEE Asian Solid-State Circuits Conference (A-SSCC)最新文献

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Range pre-selection sampling technique to reduce input drive energy for SAR ADCs 范围预选采样技术，以减少输入驱动能量的SAR adc
2017 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2017-11-08 DOI: 10.1109/ASSCC.2017.8240255
H. S. Bindra, J. Lechevallier, A. Annema, S. Louwsma, E. V. Tuijl, B. Nauta
{"title":"Range pre-selection sampling technique to reduce input drive energy for SAR ADCs","authors":"H. S. Bindra, J. Lechevallier, A. Annema, S. Louwsma, E. V. Tuijl, B. Nauta","doi":"10.1109/ASSCC.2017.8240255","DOIUrl":"https://doi.org/10.1109/ASSCC.2017.8240255","url":null,"abstract":"A Range Pre-selection Sampling (RPS) technique is introduced to reduce the input drive energy for SAR ADCs and is applied to a 10-bit 2MS/s SAR ADC in 65nm CMOS in this paper. Using the proposed RPS technique, the peak input sampling current and hence the input drive power requirement is reduced by a factor 2.4 as compared to conventional sampling (CS). Considering an ideal Class A operation for the buffer circuit driving the ADC, this translates into a minimum (theoretical) driver power consumption of 50μW for our RPS based ADC whereas it is 130μW for the conventional sampling, both much larger than the ADC power consumption of 3.25μW at 1MS/s operation. Our ADC occupies an area of 0.08 mm2 and achieves an SFDR of 64 dB, an SNDR of 55 dB with a Walden Figure of Merit, FoMw of 6.8fJ/conversion-step at up-to 2MS/s.","PeriodicalId":438242,"journal":{"name":"2017 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117064599","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A low-voltage low-offset dual strong-arm latch comparator 一种低压低偏置双强臂闩锁比较器
2017 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2017-11-01 DOI: 10.1109/ASSCC.2017.8240271
A. Papadopoulou, V. Milovanovic, B. Nikolić
{"title":"A low-voltage low-offset dual strong-arm latch comparator","authors":"A. Papadopoulou, V. Milovanovic, B. Nikolić","doi":"10.1109/ASSCC.2017.8240271","DOIUrl":"https://doi.org/10.1109/ASSCC.2017.8240271","url":null,"abstract":"A dual strong-arm (DSA) comparator is designed targeting at low-voltage operation in deeply-scaled technologies. The addition of a second regenerative latch helps reduce both offset sensitivity and offset while maintaining comparable or better performance as a conventional double-tail latch across a wide range of voltages. A large comparator offset measurement array is fabricated in a 28nm FDSOI process. The DSA offset is measured to be 8.5mV across 6 dies, approximately 30% lower than the conventional topology at iso-area and iso-capacitance conditions. It is also shown to scale well with supply and commonmode voltage, achieving up to 65% lower offset across the voltage range.","PeriodicalId":438242,"journal":{"name":"2017 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127482705","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
An element-matched band-pass delta-sigma ADC for ultrasound imaging 用于超声成像的元件匹配带通δ - σ ADC
2017 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2017-11-01 DOI: 10.1109/ASSCC.2017.8240235
M. D'Urbino, Chao Chen, Zhao Chen, Z. Chang, Jacco Ponte, Boris Lippe, M. Pertijs
{"title":"An element-matched band-pass delta-sigma ADC for ultrasound imaging","authors":"M. D'Urbino, Chao Chen, Zhao Chen, Z. Chang, Jacco Ponte, Boris Lippe, M. Pertijs","doi":"10.1109/ASSCC.2017.8240235","DOIUrl":"https://doi.org/10.1109/ASSCC.2017.8240235","url":null,"abstract":"This work presents a compact ADC architecture capable of digitizing the signals received by every individual element of a 2D ultrasound transducer array. An element-matched layout of 150 μm × 150 μm is realized by exploiting each piezo-electric transducer element not only as the signal source, but also as the electro-mechanical loop-filter of a continuoustime band-pass ΔΣ ADC, thus minimizing the required circuit blocks. The transducer's frequency response, which is inherently matched with the signal bandwidth of interest, provides noise shaping to the ADC. A prototype chip has been fabricated in a 0.18 μm CMOS technology, featuring 20 ADCs located directly underneath a 150 μm-pitch piezo-electric transducer array fabricated on top of the chip. Each ADC, clocked at 200 MHz, consumes 800 μψ from a 1.8 V supply, and achieves an SNR of 47 dB in a 75% bandwidth around a center frequency of 5 MHz. Acoustic measurements show that the ADC successfully digitizes incoming echo signals.","PeriodicalId":438242,"journal":{"name":"2017 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128807695","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A smart-offset analog LDO with 0.3V minimum input voltage and 99.1% current efficiency 一个具有0.3V最小输入电压和99.1%电流效率的智能失调模拟LDO
2017 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2017-11-01 DOI: 10.1109/ASSCC.2017.8240268
Saurabh Chaubey, R. Harjani
{"title":"A smart-offset analog LDO with 0.3V minimum input voltage and 99.1% current efficiency","authors":"Saurabh Chaubey, R. Harjani","doi":"10.1109/ASSCC.2017.8240268","DOIUrl":"https://doi.org/10.1109/ASSCC.2017.8240268","url":null,"abstract":"In this paper we present the first fully integrated analog LDO (low dropout regulator) for sub-0.5V supply voltages. The LDO can operate from 0.3V-to-1.0V input voltage, and can sustain a load variation of 10mA-to-100mA at 1.0V input and 5mA-to-25mA at 0.3V input. It achieves a peak 99.1% current efficiency for a 100mA load at 0.9V output voltage. In order to realize the gate drive at sub-0.5V supply voltages, we introduce a negative charge pump based adaptive offset before the pass FET which provides gate-source headroom at input operation voltages normally reserved for digital LDOs. The smart-adaptive-negative offset voltage follows a 0.5–0.5xVdd scheme to accommodate a wide range of input voltages while providing the necessary extra gate drive for the power FET at low inputs. The 32 phase charge pump runs at a frequency of 3GHz with a ripple of ∼ 3mV. The prototype was fabricated in TSMC's 65nm GP CMOS.","PeriodicalId":438242,"journal":{"name":"2017 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"556 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123311574","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A 173–200 GHz quadrature voltage-controlled oscillator in 130 nm SiGe BiCMOS 130 nm SiGe BiCMOS中173-200 GHz正交压控振荡器
2017 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2017-11-01 DOI: 10.1109/ASSCC.2017.8240225
Paul Stärke, V. Riess, C. Carta, F. Ellinger
{"title":"A 173–200 GHz quadrature voltage-controlled oscillator in 130 nm SiGe BiCMOS","authors":"Paul Stärke, V. Riess, C. Carta, F. Ellinger","doi":"10.1109/ASSCC.2017.8240225","DOIUrl":"https://doi.org/10.1109/ASSCC.2017.8240225","url":null,"abstract":"This work presents a fundamental-mode voltage-controlled oscillator (VCO) realized in a 130 nm SiGe BiCMOS process for operation up to 200 GHz. The implemented topology is derived from a feedback phase shifter design, which includes a wideband passive polyphase filter based on 90° and 180° transmission line couplers and a variable-gain active combiner. The fabricated circuit achieves a very large frequency tuning range of 173–200 GHz with a phase noise down to −85dBc/Hz at 10 MHz offset around 188 GHz. As an unique feature this topology allows the simultaneous generation of 90° quadrature signals, which are amplified by an additional single-stage output buffer. The power level of both output signals over a wide bandwidth is −3 dBm each, with a total dc power consumption of 27.7 mW for the oscillator core and 10.3 mW per buffer.","PeriodicalId":438242,"journal":{"name":"2017 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126238901","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A 16-channel TDM analog front-end with enhanced system CMRR for wearable dry EEG recording 一种带增强系统CMRR的16通道TDM模拟前端，用于可穿戴干式脑电图记录
2017 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2017-11-01 DOI: 10.1109/ASSCC.2017.8240209
T. Tang, W. Goh, Lei Yao, Yuan Gao
{"title":"A 16-channel TDM analog front-end with enhanced system CMRR for wearable dry EEG recording","authors":"T. Tang, W. Goh, Lei Yao, Yuan Gao","doi":"10.1109/ASSCC.2017.8240209","DOIUrl":"https://doi.org/10.1109/ASSCC.2017.8240209","url":null,"abstract":"This paper presents a 16-channel analog front-end (AFE) for wearable dry EEG recording. A novel AFE architecture that combines time division multiplexing (TDM) and chopping stabilization (CS) to improve the system common mode rejection ratio (CMRR) and the input-referred noise is proposed. With TDM, the reference electrode is connected to single channel input during its time slot to avoid the CMRR degradation caused by input impedance imbalance. Furthermore, the 2nd stage programmable gain amplifier (PGA) is shared among multiple channels, leading to significant reduction in both power consumption and chip area. In addition, input impedance boosting loop and DC servo-loop are included to boost the input impedance and cancel the input DC offset. Implemented in a 0.18-pm CMOS process, the proposed AFE shows 0.63 pVrms input-referred noise integrated from 0.5 Hz to 100 Hz and 560 ΜΩ input impedance at 50 Hz. The measured AFE intrinsic CMRR is 89 dB and the system CMRR is 82 dB, which is a 40 dB improvement compared to the conventional architecture. The AFE chip consumes merely 1.5 pW per channel under the 1 V supply voltage.","PeriodicalId":438242,"journal":{"name":"2017 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129370008","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A 0.6-V 200-kbps 429-MHz ultra-low-power FSK transceiver in 90-nm CMOS 基于90纳米CMOS的0.6 v 200-kbps 429-MHz超低功耗FSK收发器
2017 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2017-11-01 DOI: 10.1109/ASSCC.2017.8240249
Chun-Yuan Chiu, Zhen-Cheng Zhang, Tsung-Hsien Lin
{"title":"A 0.6-V 200-kbps 429-MHz ultra-low-power FSK transceiver in 90-nm CMOS","authors":"Chun-Yuan Chiu, Zhen-Cheng Zhang, Tsung-Hsien Lin","doi":"10.1109/ASSCC.2017.8240249","DOIUrl":"https://doi.org/10.1109/ASSCC.2017.8240249","url":null,"abstract":"A 0.6-V, 200-kbps, 429-MHz ultra-low-power FSK transceiver (TRX) is presented. The receiver (RX) adopts a frequency-to-time based demodulator, which detects high or low frequency to determine data output level. The proposed RX achieves −85-dBm sensitivity at 0.1% BER and draws 0.146 mW. A 38.7% global efficiency, 429-MHz FSK transmitter (TX) is also reported in this paper. To remove the power-hungry sub-circuits, such as PA and PLL, the proposed TX is essentially constituted by an oscillator which drives the antenna via an impedance matching network for power conversion. The TX draws 0.39 mW and delivers −8.2-dBm output power. It achieves 38.7% global efficiency. The transceiver is fabricated in 90-nm CMOS process.","PeriodicalId":438242,"journal":{"name":"2017 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133744791","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A compact 87.1-dB DR bandwidth-scalable delta-sigma modulator based on dynamic gain-bandwidth-boosting inverter for audio applications 一种紧凑的87.1 db DR带宽可扩展δ - σ调制器，基于动态增益-带宽增强逆变器，用于音频应用
2017 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2017-11-01 DOI: 10.1109/ASSCC.2017.8240274
Young-Ha Hwang, Jun-Eun Park, D. Jeong
{"title":"A compact 87.1-dB DR bandwidth-scalable delta-sigma modulator based on dynamic gain-bandwidth-boosting inverter for audio applications","authors":"Young-Ha Hwang, Jun-Eun Park, D. Jeong","doi":"10.1109/ASSCC.2017.8240274","DOIUrl":"https://doi.org/10.1109/ASSCC.2017.8240274","url":null,"abstract":"This paper presents a compact audio delta-sigma modulator that features a scalable bandwidth to also support biomedical instrumentation such as digital hearing aids and electromyography, sustaining constant FoMS. The modulator achieves a small die area and low power consumption by exploiting the proposed dynamic gain-bandwidth-boosting (GBWB) scheme in the inverter-based class-AB OTA with minimal overhead. The modulator features 56.8 dB PSRR without any external decoupling capacitor for a power supply and 66.1 dB CMRR in the audio band by utilizing a pseudo-differential structure with the dynamic GBWB scheme. For 25 kHz bandwidth, the modulator dissipates 68 pW from a 1.8 V supply and achieves a peak SNDR of 84.0 dB, a peak SNR of 85.1 dB, and a DR of 87.1 dB, maintaining the resolution higher than 13-bit against the supply voltage variation of 0.15 V. The prototype modulator is fabricated in 0.18 pm CMOS technology, occupying an active area of 0.0939 mm2.","PeriodicalId":438242,"journal":{"name":"2017 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117162657","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Subthreshold voltage reference with nwell/psub diode leakage compensation for low-power high-temperature systems 具有nwell/psub二极管漏损补偿的亚阈值基准电压，适用于低功率高温系统
2017 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2017-11-01 DOI: 10.1109/ASSCC.2017.8240267
Inhee Lee, D. Sylvester, D. Blaauw
{"title":"Subthreshold voltage reference with nwell/psub diode leakage compensation for low-power high-temperature systems","authors":"Inhee Lee, D. Sylvester, D. Blaauw","doi":"10.1109/ASSCC.2017.8240267","DOIUrl":"https://doi.org/10.1109/ASSCC.2017.8240267","url":null,"abstract":"This paper proposes a voltage reference operating up to 170 °C for low-power high-temperature systems. The proposed circuit buffers body voltages to avoid degradation of temperature coefficient from nwell/psub diode leakage. For low power overhead, it measures the diode leakage and adaptively adjusts the bias current of the buffers. This enables low power consumption at low temperature, which can allow an energy harvester to recharge a battery in the target system. Prototype chips, fabricated in a 180 nm CMOS process, show a ±3σ inaccuracy of 3.4% from 0 °C to 170 °C after single trim at 80 °C and a line sensitivity of 0.088 %/V from 1.8 V to 3.6 V. It consumes 76.3 pA at room temperature and 177 nA at 170 °C from 1.8 V.","PeriodicalId":438242,"journal":{"name":"2017 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128652580","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
An ultra-low power 169-nA 32.768-kHz fractional-N PLL 超低功耗169-nA 32.768 khz分数n锁相环
2017 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2017-11-01 DOI: 10.1109/ASSCC.2017.8240212
Chun-Yu Lin, T. Wang, Tzu-Hsuan Liu, Tsung-Hsien Lin
{"title":"An ultra-low power 169-nA 32.768-kHz fractional-N PLL","authors":"Chun-Yu Lin, T. Wang, Tzu-Hsuan Liu, Tsung-Hsien Lin","doi":"10.1109/ASSCC.2017.8240212","DOIUrl":"https://doi.org/10.1109/ASSCC.2017.8240212","url":null,"abstract":"This paper presents an ultra-low power 32.768-kHz fractional-N phase-locked loop (PLL). Several circuit techniques are adopted to facilitate low-power operation. A duty-cycled control scheme is proposed to turn off the charge pump intermittently for energy saving. In the VCO, a near-off switch is applied to implement a large resistor, leading to a lower power consumption and smaller chip area. Furthermore, the digital power consumption is reduced by operating the digital circuits at a lower supply voltage generated from an on-chip voltage regulator. This PLL is fabricated in the TSMC 180-nm CMOS process with a core area of 0.116 mm2. Its current consumption is 169 nA from a 1-V supply. The measured peak-to-peak cycle-to-cycle jitter is 529.4 ns.","PeriodicalId":438242,"journal":{"name":"2017 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127465062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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