2017 IEEE Asian Solid-State Circuits Conference (A-SSCC)最新文献

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An area-efficient amplifier-less digitally-controlled li-ion battery charger in 0.35μm CMOS 一种0.35μm CMOS的面积高效无放大器数字控制锂离子电池充电器
2017 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2017-11-01 DOI: 10.1109/ASSCC.2017.8240210
Sheng-Ying Lin, Tsung-Hsien Lin
{"title":"An area-efficient amplifier-less digitally-controlled li-ion battery charger in 0.35μm CMOS","authors":"Sheng-Ying Lin, Tsung-Hsien Lin","doi":"10.1109/ASSCC.2017.8240210","DOIUrl":"https://doi.org/10.1109/ASSCC.2017.8240210","url":null,"abstract":"In this paper, an amplifier-less digitally-controlled lithium-ion (Li-Ion) battery charger is presented. Owing to the digitally-controlled technique, the proposed charger eliminates all analog circuits and reduces the size of the power transistor. Hence, the proposed charger features a simple circuit structure and a small chip area. Additionally, this charger provides essential operations including constant-current (CC) and constant-voltage (CV) modes. The proposed charger is implemented in the TSMC 0.35-pm CMOS process with a 5-V power supply. The output voltage is 4.2 V, and the charging current in CC mode is 600 mA with an area of only 0.768 mm2.","PeriodicalId":438242,"journal":{"name":"2017 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129075264","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
14nm Broadwell Xeon® processor family: Design methodologies and optimizations 14纳米Broadwell至强处理器系列:设计方法和优化
2017 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2017-11-01 DOI: 10.1109/ASSCC.2017.8240205
Mahesh K. Kumashikar, S. Bendi, S. Nimmagadda, A. Deka, Anil Agarwal
{"title":"14nm Broadwell Xeon® processor family: Design methodologies and optimizations","authors":"Mahesh K. Kumashikar, S. Bendi, S. Nimmagadda, A. Deka, Anil Agarwal","doi":"10.1109/ASSCC.2017.8240205","DOIUrl":"https://doi.org/10.1109/ASSCC.2017.8240205","url":null,"abstract":"This paper provides details on the new Broadwell server product family designed on 14nm Intel process. This was the first Xeon® server product on this process node. Low power, density optimized product, Broadwell-DE, has upto 8 dual-threaded 64b Broadwell cores [1], 12MB L3 cache, 2 10GT/s Ethernet KR lanes, 2 DDR4–2400MHz memory channels and 24 8GT/s PCIe lanes. Broadwell-SP, a high performance server CPU, has upto 24 dualthreaded cores, 60MB L3 cache, 4 DDR4 channels and 48 PCIe lanes. While introducing servers with varying segment types on a lead process node provides business advantages, it entails designs ability to operate across larger window of operation especially on evolving process collaterals. This paper shows a case study of server chips on 14nm process node [2], and methodologies that were used to debug and productize. The paper will show silicon results which support the strength of the methodology.","PeriodicalId":438242,"journal":{"name":"2017 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123773650","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Dual-loop 2-step ZQ calibration for dedicated power supply voltage in LPDDR4 SDRAM LPDDR4 SDRAM专用电源电压的双环两步ZQ校准
2017 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2017-11-01 DOI: 10.1109/ASSCC.2017.8240239
Chang-Kyo Lee, Junha Lee, Kiho Kim, Jin-Seok Heo, Gil-Hoon Cha, Jin-Hyeok Baek, Daesik Moon, Yoon-Joo Eom, Tae-Sung Kim, Hyunyoon Cho, Y. Son, Seonghwan Kim, Jong-Wook Park, Sewon Eom, Si-Hyeong Cho, Young-Ryeol Choi, Seungseob Lee, Kyoung-Soo Ha, Youngseok Kim, Bo-Tak Lim, Dae-Hee Jung, Eungsung Seo, Kyoung-Ho Kim, Yoon-Gyu Song, Youn-Sik Park, T. Oh, Seung-Jun Bae, Indal Song, S. Hyun, Joonbae Park, H. Kwon, Y. Sohn, J. Choi, Kwang-il Park, Seong-Jin Jang
{"title":"Dual-loop 2-step ZQ calibration for dedicated power supply voltage in LPDDR4 SDRAM","authors":"Chang-Kyo Lee, Junha Lee, Kiho Kim, Jin-Seok Heo, Gil-Hoon Cha, Jin-Hyeok Baek, Daesik Moon, Yoon-Joo Eom, Tae-Sung Kim, Hyunyoon Cho, Y. Son, Seonghwan Kim, Jong-Wook Park, Sewon Eom, Si-Hyeong Cho, Young-Ryeol Choi, Seungseob Lee, Kyoung-Soo Ha, Youngseok Kim, Bo-Tak Lim, Dae-Hee Jung, Eungsung Seo, Kyoung-Ho Kim, Yoon-Gyu Song, Youn-Sik Park, T. Oh, Seung-Jun Bae, Indal Song, S. Hyun, Joonbae Park, H. Kwon, Y. Sohn, J. Choi, Kwang-il Park, Seong-Jin Jang","doi":"10.1109/ASSCC.2017.8240239","DOIUrl":"https://doi.org/10.1109/ASSCC.2017.8240239","url":null,"abstract":"This paper presents a dual-loop 2-step ZQ calibration scheme with 20nm DRAM process to support dedicated supply voltage (VDD, VDDQ). The proposed calibration scheme maintains a target value of on-die termination (ODT) in DQ/CA regardless of the supply-voltage variations which are caused by dynamic voltage frequency switching (DVFS) and alleviates the calibration time which is increased by insertion of additional CA calibration. The offset of a comparator is averaged out by fraction-referred input switching-then-averaging scheme (FISA). And code-referred periodic ZQ update (CPZU) scheme can track the VT variation while minimizing the interference.","PeriodicalId":438242,"journal":{"name":"2017 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131145532","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 93μW 11Mbps wireless vital signs monitoring SoC with 3-lead ECG, bio-impedance, and body temperature 一个93μW 11Mbps无线生命体征监测SoC,具有3导联心电图、生物阻抗和体温
2017 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2017-11-01 DOI: 10.1109/ASSCC.2017.8240208
Yuxuan Luo, Kok-Hin Teng, Yongfu Li, Wei Mao, C. Heng, Y. Lian
{"title":"A 93μW 11Mbps wireless vital signs monitoring SoC with 3-lead ECG, bio-impedance, and body temperature","authors":"Yuxuan Luo, Kok-Hin Teng, Yongfu Li, Wei Mao, C. Heng, Y. Lian","doi":"10.1109/ASSCC.2017.8240208","DOIUrl":"https://doi.org/10.1109/ASSCC.2017.8240208","url":null,"abstract":"This paper presents an integrated wireless multiple sensors System-on-Chip (SoC) for healthcare including 3-lead ECG, bio-impedance (Bio-Z), and body temperature. To allow continuous and real-time monitoring, the SoC has included a multi-channel reconfigurable QPSK/BfSK transmitter (TX) to accommodate different power-constraint conditions. Fabricated in 130nm CMOS technology with a total die area of 6.25mm2, our SoC only consumes 93μW with 1% duty-cycling protocol in 0.9V supply.","PeriodicalId":438242,"journal":{"name":"2017 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134176242","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
A 10kHz-BW 93.7dB-SNR chopped ΔΣ ADC with 30V input CM range and 115dB CMRR at 10kHz 10kHz- bw 93.7dB-SNR斩波ΔΣ ADC,输入CM范围为30V,在10kHz时CMRR为115dB
2017 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2017-11-01 DOI: 10.1109/ASSCC.2017.8240213
Long Xu, J. Huijsing, K. Makinwa
{"title":"A 10kHz-BW 93.7dB-SNR chopped ΔΣ ADC with 30V input CM range and 115dB CMRR at 10kHz","authors":"Long Xu, J. Huijsing, K. Makinwa","doi":"10.1109/ASSCC.2017.8240213","DOIUrl":"https://doi.org/10.1109/ASSCC.2017.8240213","url":null,"abstract":"This paper presents a 15-bit ΔΣ ADC with 10kHz-BW which can handle 30V CM voltages with high AC CMRR (in excess of 115dB at 10kHz) while operating from a 1.8 V supply. An HV capacitively-coupled chopper at its input enables the accurate sampling of input signals beyond the supply rails. Chopping is used to mitigate the ADC's offset and to enhance its CMRR, especially at high frequencies.","PeriodicalId":438242,"journal":{"name":"2017 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132137608","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A low-power PAM4 receiver using 1/4-rate sampling decoder with adaptive variable-gain rectification 一种低功耗PAM4接收机,采用1/4速率采样解码器和自适应可变增益整流
2017 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2017-11-01 DOI: 10.1109/ASSCC.2017.8240221
Guang Zhu, Quan Pan, John Zhuang, C. Zhi, C. Yue
{"title":"A low-power PAM4 receiver using 1/4-rate sampling decoder with adaptive variable-gain rectification","authors":"Guang Zhu, Quan Pan, John Zhuang, C. Zhi, C. Yue","doi":"10.1109/ASSCC.2017.8240221","DOIUrl":"https://doi.org/10.1109/ASSCC.2017.8240221","url":null,"abstract":"This paper presents a 1/4-rate PAM4 receiver employing a sampling decoder with an adaptive variable-gain rectifier (AVGR) to achieve a bit efficiency of 1.38 pJ/bit. By concurrently performing gain adaptation and amplitude rectification for decoding the least significant bit (LSB), the proposed decoder greatly reduces power consumption compared with the conventional full-rate topology using three comparators. The sense amplifier (SA) in the AVGR is designed to have large gain and wide programmability in order to accommodate wide PAM4 input dynamic range (DR) while using a single constant reference voltage for decoding. Experimental results verify that the receiver IC, implemented in SMIC 28-nm high-k CMOS process, can receive and decoder a 24-Gb/s 190-mVpp PAM4 signal at a BER of 10−11.","PeriodicalId":438242,"journal":{"name":"2017 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132129440","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A −245 dB FOM 48 fs rms jitter semi-digital PLL with intrinsic temperature compensation in 130 nm CMOS −245db FOM 48秒频抖动半数字锁相环,内置温度补偿130nm CMOS
2017 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2017-11-01 DOI: 10.1109/ASSCC.2017.8240282
J. Anders, S. Bader, M. Dietl, P. Sareen, G. Rombach, S. Tambouris, M. Ortmanns
{"title":"A −245 dB FOM 48 fs rms jitter semi-digital PLL with intrinsic temperature compensation in 130 nm CMOS","authors":"J. Anders, S. Bader, M. Dietl, P. Sareen, G. Rombach, S. Tambouris, M. Ortmanns","doi":"10.1109/ASSCC.2017.8240282","DOIUrl":"https://doi.org/10.1109/ASSCC.2017.8240282","url":null,"abstract":"In this paper, we present a temperature compensated semi-digital integer-N PLL realized in a standard 130 nm CMOS technology, which achieves 48 fs rms phase jitter and a FOM of −245 dB. The presented design improves the phase noise performance of previously presented semi-digital PLLs by replacing the ring oscillator VCO by a semi-digitally tuned LC-tank VCO. In contrast to mostly digital PLLs, the presented architecture uses simple linear analog circuitry, removing the need for non-linear bang-bang PFDs or high speed oversampled ΣΔ-modulators.","PeriodicalId":438242,"journal":{"name":"2017 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117214171","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 65nm 376nA 0.4V linear classifier using time-based matrix-multiplying ADC with non-linearity aware training 采用基于时间的矩阵乘法ADC和非线性感知训练的65nm 376nA 0.4V线性分类器
2017 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2017-11-01 DOI: 10.1109/ASSCC.2017.8240278
A. Anvesha, A. Raychowdhury
{"title":"A 65nm 376nA 0.4V linear classifier using time-based matrix-multiplying ADC with non-linearity aware training","authors":"A. Anvesha, A. Raychowdhury","doi":"10.1109/ASSCC.2017.8240278","DOIUrl":"https://doi.org/10.1109/ASSCC.2017.8240278","url":null,"abstract":"A 6-bit time-based folding matrix multiplication technique for support vector machine (SVM) classification is proposed. A voltage controlled oscillator (VCO) based analog-to-digital converter (ADC) performs in-situ matrix multiplications (MM) along with analog to digital conversion. It also offers a low supply voltage of operation (down to 0.4V) and an input range of 0.8V, drawing a total of 376nA of current. We propose a technique to extend the input range of the VCO based ADC using a folding technique. The classifier is trained considering the non-linearity of the VCO, which results in 5X lower power at iso-accuracy. An accuracy of 93% is achieved with adaboost at the digital back-end with linear SVM as the weak classifier.","PeriodicalId":438242,"journal":{"name":"2017 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"142 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116393941","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 0.44V-1.1V 9-transistor transition-detector and half-path error detection technique for low power applications 用于低功耗应用的0.44V-1.1V 9晶体管过渡检测器和半路误差检测技术
2017 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2017-11-01 DOI: 10.1109/ASSCC.2017.8240252
Xinchao Shang, Weiwei Shan, Longxing Shi, Xing Wan, Jun Yang
{"title":"A 0.44V-1.1V 9-transistor transition-detector and half-path error detection technique for low power applications","authors":"Xinchao Shang, Weiwei Shan, Longxing Shi, Xing Wan, Jun Yang","doi":"10.1109/ASSCC.2017.8240252","DOIUrl":"https://doi.org/10.1109/ASSCC.2017.8240252","url":null,"abstract":"To reduce conservative timing margin, many timing-error detection techniques by monitoring selected critical paths had been proposed. However, traditional adaptive methods incur significant area overheads and cannot prevent the error that is forming in the current clock cycle. In this paper, a low-overhead Transition-Detector (TD) with a 9-transistor current sensing circuit is proposed. TDs are inserted at the half-path point of the critical path, so that the timing error in the current clock cycle can be prevented. To solve the increasing problems of monitoring paths due to inserted point deviations, a selection method of half-path insertion point is proposed. The proposed method effectively reduces the number of inserted TDs by up to 69% compared with the number of monitors inserted at path endpoints. Test chips employing the proposed design approach are fabricated in 40nm CMOS. Silicon measurements demonstrate that the whole design has achieved up to 50.5% energy saving with 120mV additional voltage scaling compared to the conventional worst-case design at the expense of 3.1% area overhead.","PeriodicalId":438242,"journal":{"name":"2017 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125097299","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 350-mV 2.4-GHz quadrature oscillator with nearly instantaneous start-up using series LC tanks 一个350 mv 2.4 ghz正交振荡器,几乎瞬间启动,使用串联LC油箱
2017 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2017-11-01 DOI: 10.1109/ASSCC.2017.8240227
Yue Chen, M. Babaie, R. Staszewski
{"title":"A 350-mV 2.4-GHz quadrature oscillator with nearly instantaneous start-up using series LC tanks","authors":"Yue Chen, M. Babaie, R. Staszewski","doi":"10.1109/ASSCC.2017.8240227","DOIUrl":"https://doi.org/10.1109/ASSCC.2017.8240227","url":null,"abstract":"We propose a ring-based quadrature LC-tank oscillator for Internet-of-Things (IoT) that can operate under a 350-mV supply voltage of energy harvesters. The oscillator is based on a series LC tank, with additional control circuitry to realize a nearly instantaneous start-up of one/two RF cycles to facilitate a deeply duty-cycled burst-mode operation of IoT. Fabricated in TSMC 28nm CMOS, the prototype consumes less than 1.3mW from 350mV supply and 0.07mm2 in area, while achieving phase noise of better than −118dBc/Hz @3MHz. Frequency tuning range is 2.24∼2.61GHz.","PeriodicalId":438242,"journal":{"name":"2017 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125503320","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
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