A 0.44V-1.1V 9-transistor transition-detector and half-path error detection technique for low power applications

Xinchao Shang, Weiwei Shan, Longxing Shi, Xing Wan, Jun Yang
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引用次数: 3

Abstract

To reduce conservative timing margin, many timing-error detection techniques by monitoring selected critical paths had been proposed. However, traditional adaptive methods incur significant area overheads and cannot prevent the error that is forming in the current clock cycle. In this paper, a low-overhead Transition-Detector (TD) with a 9-transistor current sensing circuit is proposed. TDs are inserted at the half-path point of the critical path, so that the timing error in the current clock cycle can be prevented. To solve the increasing problems of monitoring paths due to inserted point deviations, a selection method of half-path insertion point is proposed. The proposed method effectively reduces the number of inserted TDs by up to 69% compared with the number of monitors inserted at path endpoints. Test chips employing the proposed design approach are fabricated in 40nm CMOS. Silicon measurements demonstrate that the whole design has achieved up to 50.5% energy saving with 120mV additional voltage scaling compared to the conventional worst-case design at the expense of 3.1% area overhead.
用于低功耗应用的0.44V-1.1V 9晶体管过渡检测器和半路误差检测技术
为了减小保守时间裕度,人们提出了许多通过监测选定的关键路径来检测时间误差的方法。然而,传统的自适应方法会产生大量的面积开销,并且不能防止在当前时钟周期中形成的误差。本文提出了一种具有9晶体管电流传感电路的低开销过渡检测器(TD)。在关键路径的半路点插入td,可以防止当前时钟周期的定时误差。为解决由于插入点偏差导致的路径监测问题,提出了一种半路径插入点选择方法。与在路径端点插入的监视器数量相比,所提出的方法有效地减少了插入td的数量,最多可减少69%。采用所提出的设计方法的测试芯片在40nm CMOS上制造。硅测量表明,与传统的最坏情况设计相比,整个设计以3.1%的面积开销为代价,在120mV的额外电压缩放下实现了高达50.5%的节能。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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