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A 0.5 V 12-bit SAR ADC using adaptive timedomain comparator with noise optimization 采用自适应时域比较器和噪声优化的0.5 V 12位SAR ADC
2017 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2017-11-01 DOI: 10.1109/ASSCC.2017.8240254
Chen-Che Kao, Sung-En Hsieh, C. Hsieh
{"title":"A 0.5 V 12-bit SAR ADC using adaptive timedomain comparator with noise optimization","authors":"Chen-Che Kao, Sung-En Hsieh, C. Hsieh","doi":"10.1109/ASSCC.2017.8240254","DOIUrl":"https://doi.org/10.1109/ASSCC.2017.8240254","url":null,"abstract":"This paper presents a low voltage and power efficient 12-bit successive-approximation register (SAR) analog-to-digital converter (ADC). The proposed adaptive time-domain (ATD) comparator automatically adjusts its input-referred noise performance according to the intermediate residual input level (ΔVin) during conversion. Considering the noise requirement of 12-bit SAR ADC, the proposed implementation effectively reduces the comparator power consumption by 50% compared with the conventional approach. The prototyped ADC is fabricated in 90nm CMOS technology with a core area of 0.109mm2. At 0.5 V supply voltage and 150-to-250kS/s sampling rate with a Nyquist input, the implemented ADC achieves a SNDR of 63.8 to 66.3 dB with a corresponding ENOB of 10.3 to 10.71 bits. The resulting figure-of-merit (FoM) are 4.52 to 4.82 fJ/conversion-step.","PeriodicalId":438242,"journal":{"name":"2017 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122843275","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A 1.5fJ/conv-step 10b 100kS/s SAR ADC with gain-boosted dynamic comparator 带增益增强动态比较器的1.5fJ/反步10b 100kS/s SAR ADC
2017 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2017-11-01 DOI: 10.1109/ASSCC.2017.8240258
Xiyuan Tang, Long Chen, Jeonggoo Song, Nan Sun
{"title":"A 1.5fJ/conv-step 10b 100kS/s SAR ADC with gain-boosted dynamic comparator","authors":"Xiyuan Tang, Long Chen, Jeonggoo Song, Nan Sun","doi":"10.1109/ASSCC.2017.8240258","DOIUrl":"https://doi.org/10.1109/ASSCC.2017.8240258","url":null,"abstract":"This paper presents a power-efficient 10-bit SAR ADC. A novel comparator topology with a dynamic common-gate stage is proposed to increase the pre-amplification gain under a low power supply voltage, thereby reducing noise and offset. Statistical estimation and loading switching techniques are synergically combined to further improve the energy efficiency. Moreover, the SAR sequencer and clock generator share only a single dynamic DFF chain to reduce the digital power. A 40nm CMOS prototype achieves a Walden FoM of 1.5fJ/conversion-step while operating at 100kS/s from a 0.5V supply.","PeriodicalId":438242,"journal":{"name":"2017 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"145 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114417416","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
A 172dB-FoM pipelined SAR ADC using a regenerative amplifier with self-timed gain control and mixed-signal background calibration 采用自定时增益控制和混合信号背景校准的再生放大器的172dB-FoM流水式SAR ADC
2017 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2017-11-01 DOI: 10.1109/ASSCC.2017.8240275
Miguel Gandara, P. Gulati, Nan Sun
{"title":"A 172dB-FoM pipelined SAR ADC using a regenerative amplifier with self-timed gain control and mixed-signal background calibration","authors":"Miguel Gandara, P. Gulati, Nan Sun","doi":"10.1109/ASSCC.2017.8240275","DOIUrl":"https://doi.org/10.1109/ASSCC.2017.8240275","url":null,"abstract":"A scaling-friendly and PVT-robust pipelined SAR ADC reusing the first-stage comparator as a regenerative residue amplifier is proposed in this work. A low-power self-timed gain control block is combined with a mixed-signal background calibration to ensure a stable amplifier gain across PVT variation. A 130nm CMOS prototype achieves a peak Walden FoM of 9.2 fJ/conv-step and a Schreier FoM of 172 dB.","PeriodicalId":438242,"journal":{"name":"2017 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115140298","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A 7GHz-bandwidth 31.5 GHz FMCW-PLL with novel twin-VCOs structure in 65nm CMOS 一种新型双vco结构的7ghz带宽31.5 GHz fmcw锁相环
2017 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2017-11-01 DOI: 10.1109/ASSCC.2017.8240281
Shunli Ma, Jili Sheng, Ning Li, Junyan Ren
{"title":"A 7GHz-bandwidth 31.5 GHz FMCW-PLL with novel twin-VCOs structure in 65nm CMOS","authors":"Shunli Ma, Jili Sheng, Ning Li, Junyan Ren","doi":"10.1109/ASSCC.2017.8240281","DOIUrl":"https://doi.org/10.1109/ASSCC.2017.8240281","url":null,"abstract":"This paper describes a novel fully integrated 35GHz frequency modulated continuous wave (FMCW) PLL with twins-VCO to 7GHz sweeping bandwidth. The proposed FMCW PLL is composed of twins-VCOs, SDM modulator and waveform generator. A novel frequency sweeping extension (FSE) technique is proposed to make the twin-VCOs take turns to sweeping to realize wide sweeping bandwidth without sacrificing the sweeping time. The RMS frequency error of the proposed PLL is 0.9MHz and phase noise is −90dBc/Hz @1MHz. The total power consumption is around 43mW. The chip was fabricated in a 65nm LP CMOS technology. The PLL consumes an active area of 0.91mm2 and power of 43mW while operating at a 1.2 V single supply.","PeriodicalId":438242,"journal":{"name":"2017 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114227338","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
25 fJ/bit, 5Mb/s, 0.3 V true random number generator with capacitively-coupled chaos system and dual-edge sampling scheme 25fj /bit, 5Mb/s, 0.3 V真随机数发生器，电容耦合混沌系统和双边缘采样方案
2017 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2017-11-01 DOI: 10.1109/ASSCC.2017.8240216
A. Do, Xin Liu
{"title":"25 fJ/bit, 5Mb/s, 0.3 V true random number generator with capacitively-coupled chaos system and dual-edge sampling scheme","authors":"A. Do, Xin Liu","doi":"10.1109/ASSCC.2017.8240216","DOIUrl":"https://doi.org/10.1109/ASSCC.2017.8240216","url":null,"abstract":"This paper proposes a low-power, small formfactor all-digital RNG utilizing a concept of capacitive coupling between two ROs to amplify jitter and a dual-edge sampling scheme to increase the data rate. It is the most useful in battery-powered IoT applications where both energy and silicon area are critical constraints. The capacitive coupling effect with all digital circuit allows our design to operate reliably over a wide range of supply voltages. It consumes only 1.85 pJ/bit at 1V supply and 67 Mb/s, which scales down to 25 fJ/bit at 0.3 V, 5 Mb/s. Its overall FOM is 1.7×104, which is more than 3× better than existing designs.","PeriodicalId":438242,"journal":{"name":"2017 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126649222","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A wide load and voltage range switched-capacitor DC-DC converter with load-dependent configurability for DVS implementation in miniature sensors 一种宽负载和电压范围的开关电容DC-DC变换器，具有负载相关的可配置性，用于微型传感器的分布式交换机实现
2017 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2017-11-01 DOI: 10.1109/ASSCC.2017.8240232
Hassan Saif, Yongmin Lee, Minsun Kim, Hyeonjik Lee, Muhammad Bilawal Khan, Yoonmyung Lee
{"title":"A wide load and voltage range switched-capacitor DC-DC converter with load-dependent configurability for DVS implementation in miniature sensors","authors":"Hassan Saif, Yongmin Lee, Minsun Kim, Hyeonjik Lee, Muhammad Bilawal Khan, Yoonmyung Lee","doi":"10.1109/ASSCC.2017.8240232","DOIUrl":"https://doi.org/10.1109/ASSCC.2017.8240232","url":null,"abstract":"A new switched capacitor (SC) converter for powering miniature sensor systems with wide load current and output voltage ranges is proposed in this paper. By adopting a multiple-ratio SC stage and reconfigurable stage interconnect scheme, the proposed converter offers fine granularity of conversion ratios, which improves efficiency for light load operation. The multiple-leaf structure for switch size control further improves light load efficiency, while parallel stage configuration improves heavy load efficiency. Under light load (500 nA), the converter maintains an efficiency of greater than 62% with a peak efficiency of 78% over a wide voltage range (400 mV to 1.6 V). Furthermore, with an active state load of 200 μA, it maintains an efficiency of greater than 64% with a peak efficency of 72% over an output voltage range of 700 mV to 1.6 V. The effective step resolution of the proposed converter is 16 mVfrom a 4 V battery.","PeriodicalId":438242,"journal":{"name":"2017 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"406 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124320697","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A 2.56mm2 718GOPS configurable spiking convolutional sparse coding processor in 40nm CMOS 一个2.56mm2 718GOPS可配置的40nm CMOS尖峰卷积稀疏编码处理器
2017 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2017-11-01 DOI: 10.1109/ASSCC.2017.8240259
Chester Liu, Sung-gun Cho, Zhengya Zhang
{"title":"A 2.56mm2 718GOPS configurable spiking convolutional sparse coding processor in 40nm CMOS","authors":"Chester Liu, Sung-gun Cho, Zhengya Zhang","doi":"10.1109/ASSCC.2017.8240259","DOIUrl":"https://doi.org/10.1109/ASSCC.2017.8240259","url":null,"abstract":"A configurable neuro-inspired inference processor is designed as an array of neurons each operating in an independent clock domain. The processor implements a recurrent network using efficient sparse convolutions with zero-patch skipping for feedforward operations, and sparse spike-driven reconstruction for feedback operations. A globally asynchronous locally synchronous structure enables scalable design and load balancing to achieve 22% reduction in power. Fabricated in 40nm CMOS, the 2.56mm2 inference processor integrates 48 neurons, a hub and an OpenRISC processor. The chip achieves 718GOPS at 380MHz, and demonstrates applications in feature extraction from images and depth extraction from stereo images.","PeriodicalId":438242,"journal":{"name":"2017 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"6 23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123739985","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 18-to-23 GHz −253.5dB-FoM sub-harmonically injection-locked ADPLL with ILFD aided adaptive injection timing alignment technique 一种18 ~ 23 GHz−253.5dB-FoM亚谐波注入锁定ADPLL，采用ILFD辅助自适应注入定时对准技术
2017 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2017-11-01 DOI: 10.1109/ASSCC.2017.8240263
Zhao Zhang, Jincheng Yang, Liyuan Liu, P. Feng, Jian Liu, N. Wu
{"title":"A 18-to-23 GHz −253.5dB-FoM sub-harmonically injection-locked ADPLL with ILFD aided adaptive injection timing alignment technique","authors":"Zhao Zhang, Jincheng Yang, Liyuan Liu, P. Feng, Jian Liu, N. Wu","doi":"10.1109/ASSCC.2017.8240263","DOIUrl":"https://doi.org/10.1109/ASSCC.2017.8240263","url":null,"abstract":"This paper presents an 18-to-23 GHz sub-harmonically injection-locked all-digital PLL (SIL-ADPLL). It adopts the proposed injection-locked frequency divider aided adaptive injection timing alignment technique and uses a proposed (UP-DN) block to adjust the injection timing adaptively at output frequency higher than 20 GHz with low power consumption. A new pulse generator is proposed to relax the trade-off between the phase-noise suppression and the power consumption. The SIL-ADPLL is implemented in 65 nm CMOS process. Measurement results show that the covered frequency range is from 18 GHz to 23 GHz and the rms jitter integrated from 1 kHz to 100 MHz is 57.4 fs at 20 GHz output. The power consumption is 13.7 mW and the FoM is −253.5 dB. This SIL-ADPLL also shows robustness over temperature and supply variation.","PeriodicalId":438242,"journal":{"name":"2017 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"142 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131931540","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
0.5 and 1.5 THz monolithic imagers in a 65 nm CMOS adopting a VCO-based signal processing 采用基于vco的信号处理的65纳米CMOS中的0.5和1.5太赫兹单片成像仪
2017 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2017-11-01 DOI: 10.1109/ASSCC.2017.8240238
Sun-a Kim, Kyoung-Yong Choi, Dae-Woong Park, Joo-Myoung Kim, Seok-Kyun Han, Sang-Gug Lee
{"title":"0.5 and 1.5 THz monolithic imagers in a 65 nm CMOS adopting a VCO-based signal processing","authors":"Sun-a Kim, Kyoung-Yong Choi, Dae-Woong Park, Joo-Myoung Kim, Seok-Kyun Han, Sang-Gug Lee","doi":"10.1109/ASSCC.2017.8240238","DOIUrl":"https://doi.org/10.1109/ASSCC.2017.8240238","url":null,"abstract":"A new architecture of monolithic THz imager adopting a VCO-based signal processing is proposed, and the enhancement of signal-to-noise ratio is analyzed. The 0.5/1.5 THz imagers, implemented in a 65 nm CMOS, show the lower noise equivalent power (NEP) than that of the detector itself, presenting the best NEP among the state-of-the-art imagers. The fully integrated THz imagers do not require external equipment, illustrating its feasibility as a portable high resolution real-time THz camera.","PeriodicalId":438242,"journal":{"name":"2017 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130393811","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Detection of 3.0 THz wave with a detector in 65 nm standard CMOS process 用65 nm标准CMOS工艺的检测器检测3.0 THz波
2017 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2017-11-01 DOI: 10.1109/ASSCC.2017.8240248
Tong Fang, Zhao-yang Liu, Liyuan Liu, Yuan-Yuan Li, Jun-qi Liu, Jian Liu, N. Wu
{"title":"Detection of 3.0 THz wave with a detector in 65 nm standard CMOS process","authors":"Tong Fang, Zhao-yang Liu, Liyuan Liu, Yuan-Yuan Li, Jun-qi Liu, Jian Liu, N. Wu","doi":"10.1109/ASSCC.2017.8240248","DOIUrl":"https://doi.org/10.1109/ASSCC.2017.8240248","url":null,"abstract":"This paper reports a 3.0 THz detector which can detect the terahertz wave radiated by a quantum cascade laser (QCL) working at pulse mode. The detector was implemented in a 65 nm silicon CMOS process. The chip size is 1.5×l.5 mm2 including bonding pads. THz detector using FET is based on plasma wave theory proposed by Dyakonov and Shur which allows detection of THz radiations far beyond the FET devices characteristic frequency (fT). The detector was measured by means of lock-in techniques and can achieve a room-temperature responsivity of 526 V/W and a noise equivalent power (NEP) of 73 pW/Hz1/2. We acquired a high resolution image of a tooth pick by raster-scanning technique, and Ultra-fine brushes can be clearly distinguished. Our results demonstrate a promising application in low-cost CMOS THz camera for high resolution imaging.","PeriodicalId":438242,"journal":{"name":"2017 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114915484","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
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