A 2.56mm2 718GOPS configurable spiking convolutional sparse coding processor in 40nm CMOS

Abstract

A configurable neuro-inspired inference processor is designed as an array of neurons each operating in an independent clock domain. The processor implements a recurrent network using efficient sparse convolutions with zero-patch skipping for feedforward operations, and sparse spike-driven reconstruction for feedback operations. A globally asynchronous locally synchronous structure enables scalable design and load balancing to achieve 22% reduction in power. Fabricated in 40nm CMOS, the 2.56mm2 inference processor integrates 48 neurons, a hub and an OpenRISC processor. The chip achieves 718GOPS at 380MHz, and demonstrates applications in feature extraction from images and depth extraction from stereo images.