Range pre-selection sampling technique to reduce input drive energy for SAR ADCs

Abstract

A Range Pre-selection Sampling (RPS) technique is introduced to reduce the input drive energy for SAR ADCs and is applied to a 10-bit 2MS/s SAR ADC in 65nm CMOS in this paper. Using the proposed RPS technique, the peak input sampling current and hence the input drive power requirement is reduced by a factor 2.4 as compared to conventional sampling (CS). Considering an ideal Class A operation for the buffer circuit driving the ADC, this translates into a minimum (theoretical) driver power consumption of 50μW for our RPS based ADC whereas it is 130μW for the conventional sampling, both much larger than the ADC power consumption of 3.25μW at 1MS/s operation. Our ADC occupies an area of 0.08 mm2 and achieves an SFDR of 64 dB, an SNDR of 55 dB with a Walden Figure of Merit, FoMw of 6.8fJ/conversion-step at up-to 2MS/s.