A 13-bit 160MS/s pipelined subranging-SAR ADC with low-offset dynamic comparator

Abstract

A 13-bit 160MS/s hybrid ADC in 65 nm CMOS is presented in this paper. By combining the pipelined, flash and SAR architectures, a hybrid ADC architecture is proposed to improve the power efficiency. An input offset storage technique of dynamic comparator is proposed to increase the conversion linearity. A reference voltage buffer with the charge compensation is proposed to save power and reduce the decoupling capacitor. The achieved peak SNDR, SFDR, and FoM are 64.2 dB, 80.5 dBc, and 107.3 fJ/conversion-step, respectively.