On-chip spur and phase noise cancellation techniques

Abstract

Two techniques for spur and phase noise cancellation have been proposed. A fully integrated design achieves a measured spur cancellation of 15dB at 250MHz and 750MHz offset as well as phase noise cancellation from 4MHz to 200MHz offset with maximum 25dB cancellation depth for a 1-GHz clock. The proposed ideas have been verified through a fabricated 65nm CMOS prototype with power consumption of 11mW from a supply voltage of 1.2V.