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2017 IEEE Asian Solid-State Circuits Conference (A-SSCC)最新文献

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A 5.35 mW 10 MHz bandwidth CT third-order ΔΣ modulator with single Opamp achieving 79.6/84.5 dB SNDR/DR in 65 nm CMOS 5.35 mW 10 MHz带宽CT三阶ΔΣ单运放调制器，在65 nm CMOS中实现79.6/84.5 dB SNDR/DR
2017 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2017-11-01 DOI: 10.1109/ASSCC.2017.8240272
Wei Wang, Yan Zhu, Chi-Hang Chan, U. Seng-Pan, R. Martins
{"title":"A 5.35 mW 10 MHz bandwidth CT third-order ΔΣ modulator with single Opamp achieving 79.6/84.5 dB SNDR/DR in 65 nm CMOS","authors":"Wei Wang, Yan Zhu, Chi-Hang Chan, U. Seng-Pan, R. Martins","doi":"10.1109/ASSCC.2017.8240272","DOIUrl":"https://doi.org/10.1109/ASSCC.2017.8240272","url":null,"abstract":"This paper presents a power-efficient single-loop continuous-time (CT) third-order sigma delta (ΔΣ) modulator that achieves a SNDR of 79.6 dB over a 10 MHz signal bandwidth. The modulator uses a feedforward-feedback (CIFF-FB) architecture which incorporates a single amplifier biquad (SAB) and a passive integrator to realize a third-order noise shaping. We also propose a continuous-time complementary (CTC) approach for the amplifier to improve the power efficiency. To alleviate the switch driver mismatch and jitter, we introduce an adaptive latch in the DAC driver. The modulator operates at a sampling rate of 640 MHz and consumes 5.35 mW from 1.2 V and 1.8 V power supplies. It achieves a DR of 84.5 dB and a SNDR of 79.6 dB with 10 MHz signal bandwidth, resulting in a Schreier FOM of 172.3 dB or 177.2 dB based on SNDR or DR, respectively.","PeriodicalId":438242,"journal":{"name":"2017 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129645014","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
HTD: A light-weight holosymmetrical transition detector based in-situ timing monitoring technique for wide-voltage-range in 40nm CMOS HTD:一种基于40nm CMOS宽电压范围的轻量化全对称跃迁探测器原位定时监测技术
2017 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2017-11-01 DOI: 10.1109/ASSCC.2017.8240253
Wentao Dai, Weiwei Shan, Xinning Liu, Jun Yang
{"title":"HTD: A light-weight holosymmetrical transition detector based in-situ timing monitoring technique for wide-voltage-range in 40nm CMOS","authors":"Wentao Dai, Weiwei Shan, Xinning Liu, Jun Yang","doi":"10.1109/ASSCC.2017.8240253","DOIUrl":"https://doi.org/10.1109/ASSCC.2017.8240253","url":null,"abstract":"To eliminate the worst-case timing margins, a 13-transistor holosymmetrical transition detector (HTD) is proposed for use in timing variation resilient systems. The HTD achieves low overhead and wide-voltage-range operation via monitoring the discharge at the floating node of two-stage CMOS inverters. Using local detection and global clock stalling, the system is stalled immediately for one cycle when an error occurs, allowing the variation resilient technique to be integrated into any circuits without architectural changes. Plus, there is no need of an error recovery mechanism by keeping the system working at the point before the first failure (PBFF) and utilizing the time-borrowing characteristics of the latch. Applied on an 8th-order filter test chip in 40nm CMOS process, without changing the system architecture, chip's measurement results demonstrate that it improves energy efficiency by 45.6%/28.1% and throughput by 179.31%/28.2% in near-VTH (0.474V) /super-VTH (1.1V) while incurring a 4.37% area overhead compared to a baseline design.","PeriodicalId":438242,"journal":{"name":"2017 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129395466","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
EQSCALE: Energy-quality scalable feature extraction engine for Sub-mW real-time video processing with 0.55 mm2 area in 40nm CMOS EQSCALE:能源质量可扩展特征提取引擎，用于Sub-mW实时视频处理，面积为0.55 mm2，采用40nm CMOS
2017 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2017-11-01 DOI: 10.1109/ASSCC.2017.8240261
A. Alvarez, Gopalakrishnan Ponnusamy, M. Alioto
{"title":"EQSCALE: Energy-quality scalable feature extraction engine for Sub-mW real-time video processing with 0.55 mm2 area in 40nm CMOS","authors":"A. Alvarez, Gopalakrishnan Ponnusamy, M. Alioto","doi":"10.1109/ASSCC.2017.8240261","DOIUrl":"https://doi.org/10.1109/ASSCC.2017.8240261","url":null,"abstract":"An energy-quality scalable (EQSCALE) feature extraction accelerator for IoT vision applications is presented. Knobs are introduced to dynamically adjust the tradeoff between energy and feature extraction quality, leveraging the intrinsic redundancy in video frames and the robustness of object recognition against missing features. Measurements of a testchip in 40nm show 310pJ/pixel energy at nominal voltage and maximum quality, and 55.6pJ/pixel when tuned for minimum energy, while still allowing correct object recognition. The active area of the accelerator is 0.55mm2. EQSCALE enables at least 5.7X energy improvement and 1.8X area reduction over state-of-the-art accelerators. To the best of our knowledge, EQSCALE is the first feature extraction accelerator operating in the sub-mW range (0.51mW) at VGA resolution and 30 fps.","PeriodicalId":438242,"journal":{"name":"2017 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128903080","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A 10-GHz multi-purpose reconfigurable built-in self-test circuit for high-speed links 用于高速链路的10 ghz多用途可重构内置自检电路
2017 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2017-11-01 DOI: 10.1109/ASSCC.2017.8240219
Myungguk Lee, Seungho Han, J. Sim, Hong-June Park, Byungsub Kim
{"title":"A 10-GHz multi-purpose reconfigurable built-in self-test circuit for high-speed links","authors":"Myungguk Lee, Seungho Han, J. Sim, Hong-June Park, Byungsub Kim","doi":"10.1109/ASSCC.2017.8240219","DOIUrl":"https://doi.org/10.1109/ASSCC.2017.8240219","url":null,"abstract":"This paper presents a multi-purpose built-in selftest circuit to reduce large design overhead in preparing various tests of high-speed links. The proposed circuit can be configured as a pattern generator, a pseudo-random bit sequence generator, a scrambler, a descrambler, or a snapshot, all of which are frequently used in various link tests but also require significant design effort. T o reduce the large design overhead, we efficiently implemented the five aforementioned functions in a single design by sharing their common structure. A test chip was fabricated in 28-nm CMOS technology, and the five target functions were successfully verified at 10Gb/s consuming 9.27 mW. To demonstrate the usefulness of the proposed circuit, a horizontal eye and a pulse-response were also measured in-situ by utilizing the proposed circuits which were configured to conduct various different functions.","PeriodicalId":438242,"journal":{"name":"2017 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121754993","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A 16kb column-based split cell-VSS, data-aware write-assisted 9T ultra-low voltage SRAM with enhanced read sensing margin in 28nm FDSOI 采用28nm FDSOI技术，设计了一种基于16kb列的分裂单元vss、数据感知写入辅助的9T超低电压SRAM，具有增强的读感知裕度
2017 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2017-11-01 DOI: 10.1109/ASSCC.2017.8240242
M. S. M. Siddiqui, Zhao Chuan Lee, T. T. Kim
{"title":"A 16kb column-based split cell-VSS, data-aware write-assisted 9T ultra-low voltage SRAM with enhanced read sensing margin in 28nm FDSOI","authors":"M. S. M. Siddiqui, Zhao Chuan Lee, T. T. Kim","doi":"10.1109/ASSCC.2017.8240242","DOIUrl":"https://doi.org/10.1109/ASSCC.2017.8240242","url":null,"abstract":"We propose a column-based split cell-VSS (CS-CVSS) data-aware write-assisted (DAW A) 9T ultra-low voltage SRAM with enhanced read sensing margin in 28nm FDSOI technology. The proposed write-assist technique (CS-CVSS and DAWA) improve both half-select SNM and write margin. The proposed 3T low leakage read port enhances read sensing margin by minimizing bitline leakage through negative gate to source voltage. A 16kb 9T SRAM test chip demonstrates VDDMIN-Write improvement of 0.39 V and VDDMIN-Read of 0.25 V with 1.57 ps read access time. The energy of 6.72 pJ is achieved at 0.5 V.","PeriodicalId":438242,"journal":{"name":"2017 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"4 6","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120813991","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A reconfigurable analog baseband transformer for multistandard applications in 14nm FinFET CMOS 用于14nm FinFET CMOS多标准应用的可重构模拟基带变压器
2017 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2017-11-01 DOI: 10.1109/ASSCC.2017.8240202
Jongmi Lee, Jongwoo Lee, Chilun Lo, Jaehoon Lee, In-Young Lee, Byungki Han, Seunghyun Oh, T. Cho
{"title":"A reconfigurable analog baseband transformer for multistandard applications in 14nm FinFET CMOS","authors":"Jongmi Lee, Jongwoo Lee, Chilun Lo, Jaehoon Lee, In-Young Lee, Byungki Han, Seunghyun Oh, T. Cho","doi":"10.1109/ASSCC.2017.8240202","DOIUrl":"https://doi.org/10.1109/ASSCC.2017.8240202","url":null,"abstract":"This paper proposes the reconfigurable RX analog baseband transformer that supports multi-standard applications. The proposed ABB can transform its structure between a delta-sigma modulated ADC for narrow band and a baseband LPF for wide band with a simple switch configuration without extra cost. Thus, the ABB obtains efficiency in both size and power aspects. It occupies only 0.11mm2 of active area by avoiding large capacitor for narrow band filtering and consumes 1.33mW and 12.1mW in GSM and LTE40M modes, respectively.","PeriodicalId":438242,"journal":{"name":"2017 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116969177","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 1.4Mb 40-nm embedded ReRAM macro with 0.07um2 bit cell, 2.7mA/100MHz low-power read and hybrid write verify for high endurance application 1.4Mb 40 nm嵌入式ReRAM宏，具有0.07um2位单元，2.7mA/100MHz低功耗读和混合写验证，可用于高耐用性应用
2017 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2017-11-01 DOI: 10.1109/ASSCC.2017.8240203
Chia-Fu Lee, Hon-Jarn Lin, C. Lien, Y. Chih, T. Chang
{"title":"A 1.4Mb 40-nm embedded ReRAM macro with 0.07um2 bit cell, 2.7mA/100MHz low-power read and hybrid write verify for high endurance application","authors":"Chia-Fu Lee, Hon-Jarn Lin, C. Lien, Y. Chih, T. Chang","doi":"10.1109/ASSCC.2017.8240203","DOIUrl":"https://doi.org/10.1109/ASSCC.2017.8240203","url":null,"abstract":"Resistive RAM (ReRAM) is an attractive candidate for next generation embedded nonvolatile memory [1][2], with several advantages compared to conventional flash technology. First, ReRAM is a CMOS-compatible low temperature back-end of line (BEOL) memory. There is almost no mutual impact between ReRAM element and front-end CMOS devices during the wafer processing. Second, it only needs 2∼4 extra masks, resulting in lower chip cost compared to embedded flash. Third, its byte-alterability makes it capable of being used as a unified memory for storage of instruction code and real-time data. In this work, a 1.4Mb HfOx-based embedded ReRAM macro with 0.07um2 bit cell is fabricated in a 40nm CMOS process. A hybrid write-verify algorithm (HWVA) is used to tighten the resistance distribution and avoid over-write damage for achieving fast write and high endurance. Cycling test results show a write endurance of 106 cycles for the proposed HWVA. For low-power applications, a low power sensing scheme is presented for this 1.4Mb macro, achieving 100MHz read speed and 2.7mA/100MHz read current for 44-bits read operation. An area-efficient row-redundancy scheme and double-error-correction ECC are implemented for further improvement of yield and reliability.","PeriodicalId":438242,"journal":{"name":"2017 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126618998","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
A −121dBm sensitivity, 2μJ/bit Rx, 8.8μJ/bit Tx, narrowband transceiver for ARIB STD and IoT A−121dBm灵敏度，2μJ/bit Rx, 8.8μJ/bit Tx，窄带收发器，适用于ARIB STD和IoT
2017 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2017-11-01 DOI: 10.1109/ASSCC.2017.8240247
M. Raja, Zhao Bin, D. Yan, Hongbao Zhang, W. Y. Lim, Leo John Chemmanda
{"title":"A −121dBm sensitivity, 2μJ/bit Rx, 8.8μJ/bit Tx, narrowband transceiver for ARIB STD and IoT","authors":"M. Raja, Zhao Bin, D. Yan, Hongbao Zhang, W. Y. Lim, Leo John Chemmanda","doi":"10.1109/ASSCC.2017.8240247","DOIUrl":"https://doi.org/10.1109/ASSCC.2017.8240247","url":null,"abstract":"A narrowband low-power low-sensitivity, IoT TxRx compliant to ARIB STD-T-67 & T-30, is presented. It employs (1) an injection locked IQ-divider without power-hungry high speed logic gates and flip flops to generate 25% duty cycle LO that drives the mixer following a simultaneously noise and impedance matched gm-boosted LNA, and (2) A dedicated pilot-less direct automatic frequency correction of the PLL forcing the IF to be free of offset. The second feature (a) enables lowest noise bandwidth in the detector, (b) positions the signal spectrum at the center of the pass band of the high-Q IF chain away from the phase distortions in the 3-dB transition region, and (c) simplifies the base band design. Measured sensitivity is −121dBm (@4.8kbps), Rx energy efficiency is 2.81pJ/bit and Tx efficiency is 47.5%, all of which advances the state of the art, to the authors knowledge.","PeriodicalId":438242,"journal":{"name":"2017 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124717141","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A programmable RFSoC in 16nm FinFET technology for wideband communications 用于宽带通信的16nm FinFET技术的可编程RFSoC
2017 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2017-11-01 DOI: 10.1109/ASSCC.2017.8240201
B. Farley, C. Erdmann, B. Vaz, John McGrath, Edward Cullen, B. Verbruggen, R. Pelliconi, D. Breathnach, P. Lim, Ali Boumaalif, Patrick Lynch, Conrado Mesadri, D. Melinn, K. Yap, L. Madden
{"title":"A programmable RFSoC in 16nm FinFET technology for wideband communications","authors":"B. Farley, C. Erdmann, B. Vaz, John McGrath, Edward Cullen, B. Verbruggen, R. Pelliconi, D. Breathnach, P. Lim, Ali Boumaalif, Patrick Lynch, Conrado Mesadri, D. Melinn, K. Yap, L. Madden","doi":"10.1109/ASSCC.2017.8240201","DOIUrl":"https://doi.org/10.1109/ASSCC.2017.8240201","url":null,"abstract":"In this paper, we present a Programmable SoC device with monolithically integrated RF-ADCs and RF-DACs in a 16nm FinFET process. The device includes quad ARM Cortex-53 and dual ARM Cortex-R5 processing subsystem, 750K programmable logic cells, 4000 DSP slices and 4 32Gb/s serial transceivers. Each 14-bit RF-DAC operates at a sample rate of up to 6.4GS/s and can directly synthesize RF carriers up to 4GHz. Each 12-bit RF-ADC operates at a sample rate of up to 4GS/s and can directly digitize RF carriers up to 4GHz. Other RF functions generally associated with analog / RF such as complex mixing and filtering have also been integrated and implemented in the digital domain (digital-RF), enabling lower system cost and power and increased flexibility.","PeriodicalId":438242,"journal":{"name":"2017 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116344877","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
An area-efficient capacitively-coupled sensor readout circuit with current-splitting OTA and FIR-DAC 一种具有分流OTA和FIR-DAC的面积高效电容耦合传感器读出电路
2017 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2017-11-01 DOI: 10.1109/ASSCC.2017.8240215
Chih-Chan Tu, Feng-Wen Lee, Han-Chun Chen, Yu-Kai Wang, Tsung-Hsien Lin
{"title":"An area-efficient capacitively-coupled sensor readout circuit with current-splitting OTA and FIR-DAC","authors":"Chih-Chan Tu, Feng-Wen Lee, Han-Chun Chen, Yu-Kai Wang, Tsung-Hsien Lin","doi":"10.1109/ASSCC.2017.8240215","DOIUrl":"https://doi.org/10.1109/ASSCC.2017.8240215","url":null,"abstract":"An area-efficient CTDSM for sensor applications is presented. The proposed capacitively-coupled CTDSM combines the functions of precision amplifier and DSM to achieve hardware efficiency. The 1-bit quantizer with FIR-DAC improves the linearity without using DEM in multi-bit architectures or large-size analog filters. The proposed currentsplitting OTA saves the capacitor area in the first integrator stage. Fabricated in a 0.18-μm CMOS, this chip draws 70 μA (?) from a 1.8-V supply, and achieves 12-bit resolution under 2-kHz bandwidth at ±40-mV input range. The circuit area is only 0.2 mm2.","PeriodicalId":438242,"journal":{"name":"2017 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130271694","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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