A 5.35 mW 10 MHz bandwidth CT third-order ΔΣ modulator with single Opamp achieving 79.6/84.5 dB SNDR/DR in 65 nm CMOS

Abstract

This paper presents a power-efficient single-loop continuous-time (CT) third-order sigma delta (ΔΣ) modulator that achieves a SNDR of 79.6 dB over a 10 MHz signal bandwidth. The modulator uses a feedforward-feedback (CIFF-FB) architecture which incorporates a single amplifier biquad (SAB) and a passive integrator to realize a third-order noise shaping. We also propose a continuous-time complementary (CTC) approach for the amplifier to improve the power efficiency. To alleviate the switch driver mismatch and jitter, we introduce an adaptive latch in the DAC driver. The modulator operates at a sampling rate of 640 MHz and consumes 5.35 mW from 1.2 V and 1.8 V power supplies. It achieves a DR of 84.5 dB and a SNDR of 79.6 dB with 10 MHz signal bandwidth, resulting in a Schreier FOM of 172.3 dB or 177.2 dB based on SNDR or DR, respectively.