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A 51Gb/s, 320mW, PAM4 CDR with baud-rate sampling for high-speed optical interconnects 51Gb/s, 320mW, PAM4 CDR，波特率采样，用于高速光互连
2017 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2017-11-01 DOI: 10.1109/ASSCC.2017.8240223
Nan Qi, Yuhang Kang, Qi-Peng Lin, Jianxu Ma, Jingbo Shi, Bozhi Yin, Chang Liu, Rui Bai, Shang Hu, Juncheng Wang, Jiangbing Du, Lin Ma, Zuyuan He, Ming Liu, Feng Zhang, P. Chiang
{"title":"A 51Gb/s, 320mW, PAM4 CDR with baud-rate sampling for high-speed optical interconnects","authors":"Nan Qi, Yuhang Kang, Qi-Peng Lin, Jianxu Ma, Jingbo Shi, Bozhi Yin, Chang Liu, Rui Bai, Shang Hu, Juncheng Wang, Jiangbing Du, Lin Ma, Zuyuan He, Ming Liu, Feng Zhang, P. Chiang","doi":"10.1109/ASSCC.2017.8240223","DOIUrl":"https://doi.org/10.1109/ASSCC.2017.8240223","url":null,"abstract":"A quarter-rate 51Gb/s PAM4 CDR with decoded dual-NRZ outputs is presented for 400GbE optical transceivers. A baud-rate data-only sampling PD with zero-crossing integrating front-end is proposed to minimize the clock generation and distribution overhead, as well as improving the noise resilience under PAM4 low-SNR inputs. Measurement results show the CDR features 1.08ps RMS clock jitter, 3.4×10−9 PAM4 data recovery BER, and 6.27pJ/bit power efficiency.","PeriodicalId":438242,"journal":{"name":"2017 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"216 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134155308","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
An energy-efficient self-charged crystal oscillator with a quadrature-phase shifter technique 采用正交移相技术的高能效自充电晶体振荡器
2017 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2017-11-01 DOI: 10.1109/ASSCC.2017.8240214
W. Chang, Dai-En Jhou, Yu-Hong Yang, Tai-Cheng Lee
{"title":"An energy-efficient self-charged crystal oscillator with a quadrature-phase shifter technique","authors":"W. Chang, Dai-En Jhou, Yu-Hong Yang, Tai-Cheng Lee","doi":"10.1109/ASSCC.2017.8240214","DOIUrl":"https://doi.org/10.1109/ASSCC.2017.8240214","url":null,"abstract":"An energy-efficient self-charged crystal oscillator (SCXO) employing a quadrature-phase shifter is proposed to provide wide-range pulse injection timing for power consumption reduction. The passive resistors of quadrature-phase shifter can be shared by the startup circuit to save area consumption. The double-edge extractor and the low-power comparator are added to reduce the power consumption. The proposed 32.768-kHz energy-efficient SCXO, fabricated in a 40-nm CMOS technology, consumes 34.3 nW under a 1 V supply.","PeriodicalId":438242,"journal":{"name":"2017 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133610080","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 72.9-dB SNDR 20-MHz BW 2-2 discrete-time sturdy MASH delta-sigma modulator using source-follower-based integrators 72.9 db SNDR 20 mhz bw2 -2离散时间坚固MASH δ - σ调制器，采用基于源跟踪器的集成器
2017 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2017-11-01 DOI: 10.1109/ASSCC.2017.8240273
Yong-Sik Kwak, Kang-Il Cho, Ho-Jin Kim, Seunghoon Lee, G. Ahn
{"title":"A 72.9-dB SNDR 20-MHz BW 2-2 discrete-time sturdy MASH delta-sigma modulator using source-follower-based integrators","authors":"Yong-Sik Kwak, Kang-Il Cho, Ho-Jin Kim, Seunghoon Lee, G. Ahn","doi":"10.1109/ASSCC.2017.8240273","DOIUrl":"https://doi.org/10.1109/ASSCC.2017.8240273","url":null,"abstract":"This paper presents a 2-2 discrete-time sturdy multi-stage noise-shaping (SMASH) delta-sigma modulator using source-follower-based open-loop integrators. The resolution of the SMASH delta-sigma modulator is enhanced by eliminating the first-stage quantization noise from the output. Using the proposed source-follower-based open-loop integrator, the operating speed of the modulator is efficiently improved. The prototype deltasigma modulator fabricated in a 65-nm CMOS process achieves a 75.8-dB dynamic range and 72.9-dB SNDR in a 20-MHz bandwidth. The modulator occupies an active area of 0.34 mm2, and its total power consumption is 20.4 mW from a 1.2-V supply voltage operating at a 500-MHz clock frequency.","PeriodicalId":438242,"journal":{"name":"2017 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126172244","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
An 82% energy-saving change-sensing flip-flop in 40nm CMOS for ultra-low power applications 一款节能82%的40nm CMOS变化传感触发器，适用于超低功耗应用
2017 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2017-11-01 DOI: 10.1109/ASSCC.2017.8240250
Van Loi Le, Juhui Li, Alan Chang, T. T. Kim
{"title":"An 82% energy-saving change-sensing flip-flop in 40nm CMOS for ultra-low power applications","authors":"Van Loi Le, Juhui Li, Alan Chang, T. T. Kim","doi":"10.1109/ASSCC.2017.8240250","DOIUrl":"https://doi.org/10.1109/ASSCC.2017.8240250","url":null,"abstract":"In this paper, we propose a novel 24-transistor change-sensing flip-flop (CSFF) for ultra-low power applications. With the aid of an internal change-sensing unit, the proposed CSFF eliminates redundant transitions of internal clocked nodes when there is no change in the flip-flop content. No additional transistors are required compared to the conventional transmission-gate flip-flop (TGFF). Measurement results from a test chip fabricated in 40nm CMOS technology show that CSFF achieves the power reduction of 82% and 68% at 10% activity rate and 1.0V, and the C-Q delay improvement of 37% and 11% in the supply voltage range of 0.4V to 1.0V compared to TGFF and SSCFF. While achieving better power and energy efficiencies, CSFF still maintains robust functionality at ultra-low voltage operations. Measurement results also demonstrate that CSFF shows the minimum operating voltage of 0.19 V.","PeriodicalId":438242,"journal":{"name":"2017 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114665985","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A low-power dual-mode 20-Gb/s NRZ and 28-Gb/s PAM-4 voltage-mode transmitter 低功耗双模20gb /s NRZ和28gb /s PAM-4电压模式发射机
2017 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2017-11-01 DOI: 10.1109/ASSCC.2017.8240266
N. Yang, Ashkan Roshan-Zamir, Young-Hoon Song, S. Palermo
{"title":"A low-power dual-mode 20-Gb/s NRZ and 28-Gb/s PAM-4 voltage-mode transmitter","authors":"N. Yang, Ashkan Roshan-Zamir, Young-Hoon Song, S. Palermo","doi":"10.1109/ASSCC.2017.8240266","DOIUrl":"https://doi.org/10.1109/ASSCC.2017.8240266","url":null,"abstract":"A dual-mode NRZ/PAM-4 differential low-swing voltage-mode transmitter employs a quarter-rate output multiplexing architecture for low-power operation. In NRZ mode, 2-tap feedforward equalization is realized with analog replica-bias tap control that is configurable in high-performance controlled-impedance or energy-efficient impedance-modulated settings. This analog control also allows for efficient generation of the middle levels in PAM-4 operation. Fabricated in GP 65nm CMOS, the transmitter supports an output swing range of 100–400mVPpd with up to 12dB of equalization in NRZ mode and achieves energy efficiencies of 1.48 and 0.91pJ/b at 20-Gb/s NRZ and 28-Gb/s PAM-4 data rates. Operation in the NRZ energy-efficient impedance-modulation setting allows for power savings of up to 32% relative to the controlled-impedance setting.","PeriodicalId":438242,"journal":{"name":"2017 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125489288","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
A 77-GHz mixed-mode FMCW signal generator based on bang-bang phase detector 基于bang-bang鉴相器的77 ghz混模FMCW信号发生器
2017 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2017-11-01 DOI: 10.1109/ASSCC.2017.8240280
Jianfu Lin, Zheng Song, Nan Qi, W. Rhee, B. Chi
{"title":"A 77-GHz mixed-mode FMCW signal generator based on bang-bang phase detector","authors":"Jianfu Lin, Zheng Song, Nan Qi, W. Rhee, B. Chi","doi":"10.1109/ASSCC.2017.8240280","DOIUrl":"https://doi.org/10.1109/ASSCC.2017.8240280","url":null,"abstract":"A 77-GHz mixed-mode frequency-modulated continuous-wave (FMCW) signal generator is proposed based on the bang-bang phase detector (BBPD). Instead of employing a linear digital-to-time converter (DTC), a 1-bit 3rd-order singleloop ΔΣ modulator (SLDSM3) and a hybrid finite-impulse response (FIR) filter are utilized to suppress the quantization noise induced by the BBPD. Two-stage infinite-impulse response (IIR) filters are inserted into the digital loop filter (DLF) to reduce the instant variation at output, smoothing the chirp waveform during its generation. To improve the linearity around the turning-around points (TAPs) of the chirp, a type-III slope estimator with switchable polarity is employed. The prototype is implemented in 65-nm CMOS technology, with the total power consumption of 43.1 mW. Measurement results show a 77-GHz carrier with −81.7-dBc/Hz phase noise at 1-MHz offset, as well as a generated triangle chirp that features 1-ms repetition period, 1.827-GHz bandwidth and 336-kHz root-mean-square (RMS) frequency error.","PeriodicalId":438242,"journal":{"name":"2017 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130943808","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
An energy-optimized (37840, 34320) symmetric BC-BCH decoder for healthy mobile storages 用于健康移动存储的能量优化(37840,34320)对称BC-BCH解码器
2017 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2017-11-01 DOI: 10.1109/ASSCC.2017.8240243
Seokha Hwang, Jaehwang Jung, Daesung Kim, J. Ha, I. Park, Youngjoo Lee
{"title":"An energy-optimized (37840, 34320) symmetric BC-BCH decoder for healthy mobile storages","authors":"Seokha Hwang, Jaehwang Jung, Daesung Kim, J. Ha, I. Park, Youngjoo Lee","doi":"10.1109/ASSCC.2017.8240243","DOIUrl":"https://doi.org/10.1109/ASSCC.2017.8240243","url":null,"abstract":"This paper presents an energy-efficient symmetric block-wise concatenated-BCH (SBC-BCH) decoder architecture for energy-starving mobile storages. The proposed 4KB SBC-BCH code remarkably enhances the hard-decision-based error-correcting performance to defer the energy-consuming memorysensing operations for generating the soft-decision values, which are necessary to prolong the lifetime of flash memories. Thanks to the proposed powerful hard-decision code, the energy-efficient healthy memory condition is extended by 1.4 times. In addition, we introduce design methods for realizing the energy-efficiency SBC-BCH decoder. For example, the syndrome tracking allows the early start of the next decoding process, and the reordered Chien search minimizes the wasted waiting periods. Based on the proposed schemes, targeting the recent NAND flash memories, a prototype (37840, 34320) SBC-BCH decoder is realized in 65nm CMOS process. The prototype decoder achieves a throughput of 12.5 Gb/s while providing an energy efficiency of 3.56pJ/b, which is superior to the state-of-the-art ECC solutions for storages.","PeriodicalId":438242,"journal":{"name":"2017 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"109 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129664122","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A 1.5-GHz sub-sampling fractional-N PLL for spread-spectrum clock generator in 0.18-μm CMOS 一种用于0.18 μm CMOS扩频时钟发生器的1.5 ghz次采样分数n锁相环
2017 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2017-11-01 DOI: 10.1109/ASSCC.2017.8240264
Chun-Yu Lin, T. Wang, Tsung-Hsien Lin
{"title":"A 1.5-GHz sub-sampling fractional-N PLL for spread-spectrum clock generator in 0.18-μm CMOS","authors":"Chun-Yu Lin, T. Wang, Tsung-Hsien Lin","doi":"10.1109/ASSCC.2017.8240264","DOIUrl":"https://doi.org/10.1109/ASSCC.2017.8240264","url":null,"abstract":"This paper presents a fractional-N sub-sampling phase-locked loop (SSPLL) for spread-spectrum clock generator. A digital-to-time converter (DTC) is adopted to facilitate a fractional-N SSPLL. A digital calibration scheme is employed to eliminate DTC gain error. With the calibration method enabled, the PLL is successfully locked and achieves 18.98-dB EMI reduction. This PLL was fabricated in a TSMC 0.18-pm CMOS technology. The core area is 0.467 mm2. The chip dissipates 11.1 mW from a 1.8-V supply voltage.","PeriodicalId":438242,"journal":{"name":"2017 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122180271","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 5-bit 2 GS/s binary-search ADC with charge-steering comparators 一个带电荷控制比较器的5位2gs /s二值搜索ADC
2017 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2017-11-01 DOI: 10.1109/ASSCC.2017.8240256
U. Chio, Sai-Weng Sin, U. Seng-Pan, F. Maloberti, R. Martins
{"title":"A 5-bit 2 GS/s binary-search ADC with charge-steering comparators","authors":"U. Chio, Sai-Weng Sin, U. Seng-Pan, F. Maloberti, R. Martins","doi":"10.1109/ASSCC.2017.8240256","DOIUrl":"https://doi.org/10.1109/ASSCC.2017.8240256","url":null,"abstract":"This paper presents a 5-bit 2GS/s binary-search ADC. The proposed architecture prevents the use of a decoder to avoid the path delay racing between control signals and clock phases; thence the bit latency reduces to 1 single comparator delay only. We also propose a dynamic charge-steering comparator to quantize each bit quickly. Besides, we present well-balanced 1-of-N-to-Binary encoders to transform the output code with low power. This ADC consumes 3.9mW at 2GS/s in 65nm CMOS. It achieves a SNDR of 28 dB at Nyquist rate resulting in a FoM of 95 fJ /conv.-step.","PeriodicalId":438242,"journal":{"name":"2017 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127308747","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Word-line batch Vth modulation of TLC NAND flash memories for both write-hot and cold data 字行批处理TLC NAND闪存的第v次调制，可同时写入热数据和冷数据
2017 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2017-11-01 DOI: 10.1109/ASSCC.2017.8240241
Yoshiaki Deguchi, K. Takeuchi
{"title":"Word-line batch Vth modulation of TLC NAND flash memories for both write-hot and cold data","authors":"Yoshiaki Deguchi, K. Takeuchi","doi":"10.1109/ASSCC.2017.8240241","DOIUrl":"https://doi.org/10.1109/ASSCC.2017.8240241","url":null,"abstract":"Word-line Batch Vth Modulation (WBVM) is proposed as a comprehensive solution for both write-hot and cold data to improve the reliability of Triple Level Cell (TLC) NAND Flash memories. For write-hot data, WBVM Vth score modulation decreases the program-disturb errors by 49% and enhances the endurance by 1.8-times of 2D-TLC NAND Flash. On the other hand, for write-cold data, WBVM BER score modulation decreases the data-retention errors by 36% and extends the acceptable data-retention time by 2.3-times of 2D-TLC NAND Flash. For 3D vertical TLC NAND Flash memory, the data-retention errors decrease by 13% and the acceptable data-retention time is extended by 1.4-times.","PeriodicalId":438242,"journal":{"name":"2017 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115437202","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
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