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2017 IEEE Asian Solid-State Circuits Conference (A-SSCC)最新文献

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A dynamic power reduction in synchronous 2RW 8T dual-port SRAM by adjusting wordline pulse timing with same/different row access mode 同步2rw8t双端口SRAM在相同/不同行访问模式下通过调整字线脉冲时间来动态降低功耗
2017 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2017-11-01 DOI: 10.1109/ASSCC.2017.8240204
Yoshisato Yokoyama, Y. Ishii, Haruyuki Okuda, K. Nii
{"title":"A dynamic power reduction in synchronous 2RW 8T dual-port SRAM by adjusting wordline pulse timing with same/different row access mode","authors":"Yoshisato Yokoyama, Y. Ishii, Haruyuki Okuda, K. Nii","doi":"10.1109/ASSCC.2017.8240204","DOIUrl":"https://doi.org/10.1109/ASSCC.2017.8240204","url":null,"abstract":"An effective method is proposed to reduce dynamic power for synchronous 2-read/write (2RW) 8T dual-port (DP) SRAM. Adjusting the wordline (WL) pulse timing control circuit is newly introduced for both reading and writing operations. Row addresses of port-A and port-B are compared. The same row access is detected or not in each cycle, which is an inherent access mode of 2RW 8T DP SRAM. In different row access, the WL pulse width is shortened to reduce excessive bitline (BL) discharging power. A well balanced 8T DP SRAM bitcell layout is demonstrated using 40-nm technology. A test chip including 512 w × 73 b 36 kbit and 2 kw × 19 b (38 kbit) 2RW DP SRAM macros was designed and fabricated using 40-nm technology. The measured data show that reading and writing powers are reduced, respectively, by ∼7% and ∼18% using the proposed scheme.","PeriodicalId":438242,"journal":{"name":"2017 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"19 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131199482","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A 1.25pJ/bit 0.048mm2 AES core with DPA resistance for IoT devices 一个1.25pJ/bit 0.048mm2 AES核心，具有DPA电阻，用于物联网设备
2017 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2017-11-01 DOI: 10.1109/ASSCC.2017.8240217
Shengshuo Lu, Zhengya Zhang, M. Papaefthymiou
{"title":"A 1.25pJ/bit 0.048mm2 AES core with DPA resistance for IoT devices","authors":"Shengshuo Lu, Zhengya Zhang, M. Papaefthymiou","doi":"10.1109/ASSCC.2017.8240217","DOIUrl":"https://doi.org/10.1109/ASSCC.2017.8240217","url":null,"abstract":"An AES core designed for low-cost and energy-efficient IoT security applications is fabricated in a 65nm CMOS technology. A novel Dual-Rail Flush Logic (DRFL) with switching-independent power profile is used to yield intrinsic resistance against Differential Power Analysis (DPA) attacks with minimum area and energy consumption. Measurement results show that this 0.048mm2 core achieves energy consumption as low as 1.25pJ/bit while providing at least 2604x higher DPA resistance over its conventional CMOS counterpart, marking the smallest, most energy-efficient and most secure full-datapath AES core.","PeriodicalId":438242,"journal":{"name":"2017 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131989861","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A 21mW low-power recurrent neural network accelerator with quantization tables for embedded deep learning applications 用于嵌入式深度学习应用的21mW低功耗循环神经网络加速器与量化表
2017 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2017-11-01 DOI: 10.1109/ASSCC.2017.8240260
Jinmook Lee, Dongjoo Shin, H. Yoo
{"title":"A 21mW low-power recurrent neural network accelerator with quantization tables for embedded deep learning applications","authors":"Jinmook Lee, Dongjoo Shin, H. Yoo","doi":"10.1109/ASSCC.2017.8240260","DOIUrl":"https://doi.org/10.1109/ASSCC.2017.8240260","url":null,"abstract":"A 21mW low-power embedded Recurrent Neural Network (RNN) accelerator is proposed to realize the image captioning applications. The low-power RNN operation is achieved by 3 key features: 1) Quantization-table-based matrix multiplication with RNN weight quantization, 2) Dynamic quantization-table allocation scheme for balanced pipelined RNN operation, and 3) Zero-skipped RNN operation using quantization-table. The Quantization table enables the 98% reduction of the multiplier operations by replacing the multiplication to the table reference. The dynamic quantization-table allocation is used to achieve high chip-utilization efficiency over 90% by balanced pipeline operation for three variations of the RNN operation. The zero-skipped RNN operation reduces the overall 27% of required external memory bandwidth and quantization-table operations without any additional hardware cost. The proposed RNN accelerator of 1.84mm2 achieves 21mW power consumption and demonstrates its functionality on the image captioning RNN in 65nm CMOS process.","PeriodicalId":438242,"journal":{"name":"2017 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131655655","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
A 1GHz fault tolerant processor with dynamic lockstep and self-recovering cache for ADAS SoC complying with ISO26262 in automotive electronics 一款1GHz容错处理器，具有动态同步和自恢复缓存，适用于符合汽车电子ISO26262标准的ADAS SoC
2017 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2017-11-01 DOI: 10.1109/ASSCC.2017.8240279
Jinho Han, Youngsu Kwon, Yong Cheol Peter Cho, H. Yoo
{"title":"A 1GHz fault tolerant processor with dynamic lockstep and self-recovering cache for ADAS SoC complying with ISO26262 in automotive electronics","authors":"Jinho Han, Youngsu Kwon, Yong Cheol Peter Cho, H. Yoo","doi":"10.1109/ASSCC.2017.8240279","DOIUrl":"https://doi.org/10.1109/ASSCC.2017.8240279","url":null,"abstract":"We present a processing platform that implements DMR with separate clock and power sources to prevent dependent failures working with a reconfigurable cache that includes BIST with self-recovering function to detect transient faults and error prediction to prevent permanent faults. The fault tolerant processor is analyzed to be complying with the ISO26262 SOTIF for ADAS SoC which is fabricated with 28nm CMOS Technology. The single point faults metric is 99.64% with a safety mechanism.","PeriodicalId":438242,"journal":{"name":"2017 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114577284","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A high-speed DDFS MMIC with frequency, phase and amplitude modulations in 65nm CMOS 在65nm CMOS中实现频率、相位和幅度调制的高速DDFS MMIC
2017 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2017-11-01 DOI: 10.1109/ASSCC.2017.8240246
Abdel Martinez Alonso, M. Miyahara, A. Matsuzawa
{"title":"A high-speed DDFS MMIC with frequency, phase and amplitude modulations in 65nm CMOS","authors":"Abdel Martinez Alonso, M. Miyahara, A. Matsuzawa","doi":"10.1109/ASSCC.2017.8240246","DOIUrl":"https://doi.org/10.1109/ASSCC.2017.8240246","url":null,"abstract":"This paper describes a digital-mapping DDFS with a frequency tuning and amplitude resolutions of 24-bits and 10-bits respectively. This Si-CMOS-MMIC is the first solution supporting a sampling rate of 7GS/s and frequency, phase and amplitude modulations in the digital domain. It includes a 14-bits pipelined ripple-carry adder and a 10-bits high-speed multiplier for phase and amplitude modulations respectively. The worst case wideband/narrowband SFDR is 32dBc/42dBc. This system consumes 85.9mW/(GS/s) from a 1.2V power supply when the amplitude/phase modulations are enabled, resulting in a FoM of 469.6GS/s-2(SFDR/6)/W. A proof-of-concept chip with an active area of 0.23mm2 was characterized in LQFP packages.","PeriodicalId":438242,"journal":{"name":"2017 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115647798","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 2.1Gbps 12-channel transmitter with phase emphasis embedded serializer for UHD intra-panel interface 一个2.1Gbps的12通道发射机，相位强调嵌入式串行器，用于UHD面板内接口
2017 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2017-11-01 DOI: 10.1109/ASSCC.2017.8240265
Jihwan Park, Joo-Hyung Chae, Yong-Un Jeong, Jae-Whan Lee, Suhwan Kim
{"title":"A 2.1Gbps 12-channel transmitter with phase emphasis embedded serializer for UHD intra-panel interface","authors":"Jihwan Park, Joo-Hyung Chae, Yong-Un Jeong, Jae-Whan Lee, Suhwan Kim","doi":"10.1109/ASSCC.2017.8240265","DOIUrl":"https://doi.org/10.1109/ASSCC.2017.8240265","url":null,"abstract":"A 2.1Gbps 12-channel transmitter with phase emphasis embedded serializer for an intra-panel interface is presented. Phase emphasis is introduced into the final 2:1 stage of a 20:1 serializer to reduce the data-dependent jitter without increasing IO capacitance, by making the transition timing depend on previous data. This is combined with LVDS channel drivers which control the common-mode voltage and swing of the output signal over a wide range to match the condition of each channel. Using both phase and amplitude emphasis, the transmitter can compensate for channel losses exceeding 10dB, and eye jitter is reduced by 38%: phase emphasis is responsible for about half of this reduction. Fabricated in 28nm CMOS, the transmitter occupies 1.35mm2. The proposed transmitter is verified with 55-inch UHD (3840×2160) resolution TFT-LCD intra-panel interface.","PeriodicalId":438242,"journal":{"name":"2017 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129679190","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A self-powered always-on vision-based wake-up detector for wearable gesture user interfaces 用于可穿戴手势用户界面的自供电的始终打开的基于视觉的唤醒检测器
2017 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2017-11-01 DOI: 10.1109/ASSCC.2017.8240262
Suhwan Cho, Seongrim Choi, Junsik Woo, Ara Kim, Byeong-Gyu Nam
{"title":"A self-powered always-on vision-based wake-up detector for wearable gesture user interfaces","authors":"Suhwan Cho, Seongrim Choi, Junsik Woo, Ara Kim, Byeong-Gyu Nam","doi":"10.1109/ASSCC.2017.8240262","DOIUrl":"https://doi.org/10.1109/ASSCC.2017.8240262","url":null,"abstract":"Hand gesture recognition is one of the secure natural user interface (NUI) mechanisms on wearable devices since it does not reveal user's intention in public domain unlike the speech recognition. However, its energy dissipation is very demanding as it requires compute-intensive machine vision processing. Recently, wake-up detectors have been proposed to improve the energy-efficiency of always-on sensing nature of the NUI systems by switching off the main functional blocks while just keeping the wake-up detector alive during idle time. However, vision-based wake-up detectors still require power-consuming vision processing so we propose a self-powered vision wake-up detector to alleviate burdens on limited battery and thus facilitate always-on wake-up detection for the wearable gesture UIs. Our work has four key features to realize the self-powered wake-up detection; 1) imaging-harvesting dual-mode CMOS image sensor (CIS) with 0.6V 3T pixels, 2) subthreshold SRAM with disturb-free 0.3V 10T bitcells, 3) hand detection engine with modified Haar-like filters invariant to skin-colors, and 4) on-die switched capacitor DC-DC converter for lightweight system design. Thanks to the features combined, this work achieves selfpowered operation of always-on vision wake-up detection.","PeriodicalId":438242,"journal":{"name":"2017 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126464111","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 0.40pJ/cycle 981 μm2 voltage scalable digital frequency generator for SoC clocking 用于SoC时钟的0.40pJ/cycle 981 μm2电压可扩展数字频率发生器
2017 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2017-11-01 DOI: 10.1109/ASSCC.2017.8240218
M. Cochet, S. Clerc, Guénolé Lallement, F. Abouzeid, P. Roche, J. Autran
{"title":"A 0.40pJ/cycle 981 μm2 voltage scalable digital frequency generator for SoC clocking","authors":"M. Cochet, S. Clerc, Guénolé Lallement, F. Abouzeid, P. Roche, J. Autran","doi":"10.1109/ASSCC.2017.8240218","DOIUrl":"https://doi.org/10.1109/ASSCC.2017.8240218","url":null,"abstract":"This work presents an area-efficient voltage and frequency scalable clock generator for low-power digital SoC clocking. Named Direct Digital Sampling and Synthesis (DDSS), the open-loop generator implemented in 28 nm FD-SOI operates from 0.45 V to 1.1V with measured jitter from 1.7% to 5.1% UI. Its low power consumption of 0.40pJ/cycle at 57 MHz 0.5 V combined with the ability to perform fast frequency changes makes this circuit an alternative to PLLs for fast Dynamic Voltage and Frequency Scaling (DVFS) strategies in low power SoCs.","PeriodicalId":438242,"journal":{"name":"2017 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126816876","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 56Gbps PAM-4 optical receiver front-end 56Gbps PAM-4光接收器前端
2017 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2017-11-01 DOI: 10.1109/ASSCC.2017.8240220
Kuan-Lin Fu, Shen-Iuan Liu
{"title":"A 56Gbps PAM-4 optical receiver front-end","authors":"Kuan-Lin Fu, Shen-Iuan Liu","doi":"10.1109/ASSCC.2017.8240220","DOIUrl":"https://doi.org/10.1109/ASSCC.2017.8240220","url":null,"abstract":"A 56Gbps PAM-4 optical receiver front-end is presented. In order to reduce the input-referred current noise of the receiver front-end, the shunt feedback resistor Rf of the TIA is enlarged. And, the equalizer is inserted to boost the high-frequency gain and extend the bandwidth. The AGC amplifier using the proposed dB-linear VGAs is further to lower the noise. This PAM-4 optical receiver front-end is fabricated in a 40 nm CMOS process. Its power is 120mW from a supply of 1.2V excluding the output buffers. Its core area is 0.21mm2.","PeriodicalId":438242,"journal":{"name":"2017 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121681897","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A reconfigurable dual-band WiFi/BT combo transceiver with integrated 2G/BT SP3T, LNA/PA achieving concurrent receiving and wide dynamic range transmitting in 40nm CMOS 集成2G/BT SP3T、LNA/PA的可重构双频WiFi/BT组合收发器，在40nm CMOS中实现并发接收和宽动态范围发射
2017 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2017-11-01 DOI: 10.1109/ASSCC.2017.8240245
Meng-Hsiung Hung, Y. Shih, Chin-Fu Li, Wei-Kai Hong, Ming-Yeh Hsu, Chih-Hao Chen, Yu-Lun Chen, Chun-Wei Lin, Y. Chung
{"title":"A reconfigurable dual-band WiFi/BT combo transceiver with integrated 2G/BT SP3T, LNA/PA achieving concurrent receiving and wide dynamic range transmitting in 40nm CMOS","authors":"Meng-Hsiung Hung, Y. Shih, Chin-Fu Li, Wei-Kai Hong, Ming-Yeh Hsu, Chih-Hao Chen, Yu-Lun Chen, Chun-Wei Lin, Y. Chung","doi":"10.1109/ASSCC.2017.8240245","DOIUrl":"https://doi.org/10.1109/ASSCC.2017.8240245","url":null,"abstract":"This paper describes a WiFi/BT combo SoC with integrated dual-band PAs, LNAs and T/R switches, supporting concurrent receiving for improved throughput by 30% in dense networking environment of 2.4GHz ISM band and wide-range transmitting capability (>20dB) while keeping good output power accuracy and PA power efficiency. The measured 2.4GHz/5GHz WiFi 54Mbps RX sensitivity is −78.2/−78.1dBm and Pout is 21.3/19.5dBm. BT GFSK RX sensitivity is −95.3dBm and Pout is 13dBm. The chip occupies 20mm2 in 40nm 1P6M CMOS technology while RF area occupies 3.5mm2.","PeriodicalId":438242,"journal":{"name":"2017 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133240332","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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