A high-speed DDFS MMIC with frequency, phase and amplitude modulations in 65nm CMOS

Abstract

This paper describes a digital-mapping DDFS with a frequency tuning and amplitude resolutions of 24-bits and 10-bits respectively. This Si-CMOS-MMIC is the first solution supporting a sampling rate of 7GS/s and frequency, phase and amplitude modulations in the digital domain. It includes a 14-bits pipelined ripple-carry adder and a 10-bits high-speed multiplier for phase and amplitude modulations respectively. The worst case wideband/narrowband SFDR is 32dBc/42dBc. This system consumes 85.9mW/(GS/s) from a 1.2V power supply when the amplitude/phase modulations are enabled, resulting in a FoM of 469.6GS/s-2(SFDR/6)/W. A proof-of-concept chip with an active area of 0.23mm2 was characterized in LQFP packages.