Proceedings 2000 International Conference on Computer Design最新文献

Leakage power analysis and reduction during behavioral synthesis 行为合成过程中泄漏功率的分析和降低

Proceedings 2000 International Conference on Computer Design Pub Date : 2002-12-01 DOI: 10.1109/ICCD.2000.878342

K. Khouri, N. Jha

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引用次数: 122

Effective hardware-based two-way loop cache for high performance low power processors 有效的基于硬件的双向循环缓存，用于高性能低功耗处理器

Proceedings 2000 International Conference on Computer Design Pub Date : 2000-09-17 DOI: 10.1109/ICCD.2000.878315

T. Anderson, S. Agarwala

引用次数: 27

Predictive strategies for low-power RTOS scheduling 低功耗RTOS调度的预测策略

Proceedings 2000 International Conference on Computer Design Pub Date : 2000-09-17 DOI: 10.1109/ICCD.2000.878306

Pavan Kumar, M. Srivastava

引用次数: 46

Design of instruction stream buffer with trace support for X86 processors 具有跟踪支持的X86处理器指令流缓冲区的设计

Proceedings 2000 International Conference on Computer Design Pub Date : 2000-09-17 DOI: 10.1109/ICCD.2000.878299

J. Chiu, I. Huang, C. Chung

引用次数: 4

Rectilinear block placement using B*-trees 使用B*-树的直线块放置

Proceedings 2000 International Conference on Computer Design Pub Date : 2000-09-17 DOI: 10.1109/ICCD.2000.878307

G. Wu, Yun-Chih Chang, Yao-Wen Chang

引用次数: 41

Rethinking behavioral synthesis for a better integration within existing design flows 重新考虑行为综合，以便在现有设计流中更好地集成

Proceedings 2000 International Conference on Computer Design Pub Date : 2000-09-17 DOI: 10.1109/ICCD.2000.878330

W. Cesário, A. Jerraya, Z. Sugar, I. Moussa

引用次数: 0

Efficient logic optimization using regularity extraction 使用规则提取的高效逻辑优化

Proceedings 2000 International Conference on Computer Design Pub Date : 2000-09-17 DOI: 10.1109/ICCD.2000.878327

Thomas Kutzschebauch

引用次数: 22

Hybridizing and coalescing load value predictors 混合和合并负荷值预测

Proceedings 2000 International Conference on Computer Design Pub Date : 2000-09-17 DOI: 10.1109/ICCD.2000.878272

Martin Burtscher, B. Zorn

引用次数: 18

Equivalence checking combining a structural SAT-solver, BDDs, and simulation 结合结构sat求解器、bdd和仿真的等效性检查

Proceedings 2000 International Conference on Computer Design Pub Date : 2000-09-17 DOI: 10.1109/ICCD.2000.878323

Viresh Paruthi, A. Kuehlmann

{"title":"Equivalence checking combining a structural SAT-solver, BDDs, and simulation","authors":"Viresh Paruthi, A. Kuehlmann","doi":"10.1109/ICCD.2000.878323","DOIUrl":"https://doi.org/10.1109/ICCD.2000.878323","url":null,"abstract":"This paper presents a verification technique for functional comparison of large combinational circuits using a novel combination of known approaches. The idea is based on a tight integration of a structural satisfiability (SAT) solver, BDD sweeping, and random simulation; all three working on a shared graph representation of the circuit. The BDD sweeping and SAT solver are applied in an inter-twined manner both controlled by resource limits that are successively increased during each iteration. In this cooperative setting the BDD sweeping incrementally reduces the search space for the SAT solver until the problem is solved or the resource limits are exhausted. This approach improves on previous work in several ways: The integral application of the SAT solver significantly enhances the capacity and efficiency of BDD sweeping and extends its suitability for miscomparing designs. Further, the random simulation algorithm works on the compressed circuit graph and thus runs more efficiently. Our experiments demonstrate that the outlined approach is effective for a large class of equivalence checking instances by automatically adapting to the difficulty of the problem.","PeriodicalId":437697,"journal":{"name":"Proceedings 2000 International Conference on Computer Design","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123473684","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 67

An application of genetic algorithms and BDDs to functional testing 遗传算法和bdd在功能测试中的应用

Proceedings 2000 International Conference on Computer Design Pub Date : 2000-09-17 DOI: 10.1109/ICCD.2000.878268

Fabrizio Ferrandi, D. Sciuto, A. Fin, Franco Fummi

引用次数: 11