Effective hardware-based two-way loop cache for high performance low power processors

Abstract

The increasing level of system-level integration coupled with the higher clock frequency of today's processors is increasing the power consumption of VLSI integrated circuits more rapidly than improvements in IC manufacturing can reduce power consumption. This paper presents a method for reducing the power consumption of DSP processors through the introduction of a two-way decoded loop-cache. By retaining decoded instruction information from two loops, the method has been shown to eliminate an average of 83% of instruction fetches and 84% of instruction decode activity.