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Proceedings 2000 International Conference on Computer Design最新文献

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Efficient design error correction of digital circuits 数字电路的有效设计纠错
Proceedings 2000 International Conference on Computer Design Pub Date : 2000-09-17 DOI: 10.1109/ICCD.2000.878324
D. W. Hoffmann, T. Kropf
{"title":"Efficient design error correction of digital circuits","authors":"D. W. Hoffmann, T. Kropf","doi":"10.1109/ICCD.2000.878324","DOIUrl":"https://doi.org/10.1109/ICCD.2000.878324","url":null,"abstract":"Equivalence checking of two circuits is performed at several stages in the design cycle of hardware designs and various commercial equivalence checkers, mostly based on Boolean logic, are already in the market. Design Error Diagnosis and Correction (DEDC) methods come into play when equivalence checking has proven two circuits to be different. In many cases, DEDC methods can locate and correct design errors fully automatically. In this paper, we present an efficient symbolic method for automatic error correction of both combinational and synchronous sequential circuits. We first address the problem of rectifying combinational circuits and then show how the problem of rectifying sequential circuits can be reduced to a combinational problem without unrolling the combinational logic parts. In addition, we introduce several optimizations to our algorithm. All optimizations are safe, meaning that they neither affect the number of computed solutions nor do they neither affect the number of computed solutions nor do they decrease the quality of results. Our experimental results show that the discussed optimization strategies can make the rectification procedure 2 to 16 times faster than the unoptimized algorithm.","PeriodicalId":437697,"journal":{"name":"Proceedings 2000 International Conference on Computer Design","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124451202","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
A register file with transposed access mode 具有转置访问模式的寄存器文件
Proceedings 2000 International Conference on Computer Design Pub Date : 2000-09-17 DOI: 10.1109/ICCD.2000.878341
Yoochang Jung, Stefan G. Berg, Donglok Kim, Yongmin Kim
{"title":"A register file with transposed access mode","authors":"Yoochang Jung, Stefan G. Berg, Donglok Kim, Yongmin Kim","doi":"10.1109/ICCD.2000.878341","DOIUrl":"https://doi.org/10.1109/ICCD.2000.878341","url":null,"abstract":"We introduce a new register file architecture that provides both row-wise and column-wise accesses, thus allowing partitioned instructions to be used in column-wise processing without transposition overhead. This feature can accelerate 2D separable image and video processing algorithms, such as 2D convolution and 2D discrete cosine transform (DCT), by eliminating the transposition steps.","PeriodicalId":437697,"journal":{"name":"Proceedings 2000 International Conference on Computer Design","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127631475","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Minimization of ordered pseudo Kronecker decision diagrams 有序伪Kronecker决策图的最小化
Proceedings 2000 International Conference on Computer Design Pub Date : 2000-09-17 DOI: 10.1109/ICCD.2000.878329
P. Lindgren, R. Drechsler, B. Becker
{"title":"Minimization of ordered pseudo Kronecker decision diagrams","authors":"P. Lindgren, R. Drechsler, B. Becker","doi":"10.1109/ICCD.2000.878329","DOIUrl":"https://doi.org/10.1109/ICCD.2000.878329","url":null,"abstract":"The introduction of Decision Diagrams (DDs) has brought new means towards solving many of the problems involved in digital circuit design. Compactness of the representation is one key issue. Ordered Pseudo Kronecker Decision Diagrams (OPKDDs) together with the use of complemented edges is known to offer the most general ordered read-once DD representation at the bit-level, hence OPKDDs hold all minimal sized bit-level ordered DDs for a given function. This representation allows us to trade-off diagram canonicity against compactness. Ternary-OPKDDs (TOPKDDs) implicitly holds all OPKDDs for a given variable order. We state the canonicity criteria for TOPKDDs having complemented edges and develop an efficient sifting based method for their minimization. Furthermore, a heuristic minimization algorithm for OPKDDs is devised, utilizing the redundancies of Ternary-OPKDDs (TOPKDDs). Experiments on a set of MCNC benchmarks confirm the potential compactness of OPKDDs and demonstrate the efficiency of the proposed heuristics.","PeriodicalId":437697,"journal":{"name":"Proceedings 2000 International Conference on Computer Design","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128798619","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Synthesis and optimization of interface hardware between IP's operating at different clock frequencies 不同时钟频率下IP接口硬件的综合与优化
Proceedings 2000 International Conference on Computer Design Pub Date : 2000-09-17 DOI: 10.1109/ICCD.2000.878331
Bong-Il Park, Hoon Choi, I. Park, C. Kyung
{"title":"Synthesis and optimization of interface hardware between IP's operating at different clock frequencies","authors":"Bong-Il Park, Hoon Choi, I. Park, C. Kyung","doi":"10.1109/ICCD.2000.878331","DOIUrl":"https://doi.org/10.1109/ICCD.2000.878331","url":null,"abstract":"In system-on-a-chip design, interfacing of Intellectual Property (IP) blocks is one of the most important issues. Since most IPs are provided by different vendors, they have different interface schemes and different operating frequencies. In this paper, we propose a new interface synthesis method that enables one not only to handle the interface between IPs with different operating frequencies but also to minimize the hardware resource required for the interface. We have demonstrated the proposed algorithm by applying it to a real design example, MP3 decoder, and verified the IIS-to-PCI protocol converter on a real hardware system.","PeriodicalId":437697,"journal":{"name":"Proceedings 2000 International Conference on Computer Design","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133160737","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Analysis and optimization of ground bounce in digital CMOS circuits 数字CMOS电路的地弹跳分析与优化
Proceedings 2000 International Conference on Computer Design Pub Date : 2000-09-17 DOI: 10.1109/ICCD.2000.878277
P. Heydari, Massoud Pedram
{"title":"Analysis and optimization of ground bounce in digital CMOS circuits","authors":"P. Heydari, Massoud Pedram","doi":"10.1109/ICCD.2000.878277","DOIUrl":"https://doi.org/10.1109/ICCD.2000.878277","url":null,"abstract":"This paper is concerned with the analysis and optimization of the ground bounce in digital CMOS circuits. First, an analytical method for calculating the ground bounce is presented. The proposed method relies on accurate models of the short-channel MOS device and the chip-package interface parasitics. Next the effect of ground bounce on the buffer propagation delay and the optimum taper factor is discussed and a mathematical relationship for total propagation delay in the presence of the ground bounce is obtained. The effect of the on-chip decoupling capacitor on ground bounce waveform and the circuit performance is analyzed next and a closed form expression for the peak value of the differential mode component of the ground bounce in terms of on-chip decoupling capacitor is provided. Finally a design methodology for controlling the switching times of the output drivers to minimize the ground bounce is presented.","PeriodicalId":437697,"journal":{"name":"Proceedings 2000 International Conference on Computer Design","volume":"28 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131776405","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Optimal vs. heuristic approaches to context scheduling for multi-context reconfigurable architectures 多上下文可重构架构中上下文调度的最优与启发式方法
Proceedings 2000 International Conference on Computer Design Pub Date : 2000-09-17 DOI: 10.1109/ICCD.2000.878346
R. Maestre, Milagros Fernández, R. Hermida, F. Kurdahi, N. Bagherzadeh, H. Singh
{"title":"Optimal vs. heuristic approaches to context scheduling for multi-context reconfigurable architectures","authors":"R. Maestre, Milagros Fernández, R. Hermida, F. Kurdahi, N. Bagherzadeh, H. Singh","doi":"10.1109/ICCD.2000.878346","DOIUrl":"https://doi.org/10.1109/ICCD.2000.878346","url":null,"abstract":"This paper describes a methodology to efficiently obtain a solution to the problem of context scheduling for multi-context reconfigurable architectures, regarding the minimization of context loading overhead. The target applications are assumed to be periodic, since it is a typical feature of many DSP and multimedia applications. This work considers the trade-off between achievable system performance and algorithm efficiency. It has been developed as a part of an automated design environment for reconfigurable systems.","PeriodicalId":437697,"journal":{"name":"Proceedings 2000 International Conference on Computer Design","volume":"194 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114236281","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Symbolic binding for clustered VLIW ASIPs 群集VLIW ip的符号绑定
Proceedings 2000 International Conference on Computer Design Pub Date : 2000-09-17 DOI: 10.1109/ICCD.2000.878320
Satish Pillai, M. Jacome
{"title":"Symbolic binding for clustered VLIW ASIPs","authors":"Satish Pillai, M. Jacome","doi":"10.1109/ICCD.2000.878320","DOIUrl":"https://doi.org/10.1109/ICCD.2000.878320","url":null,"abstract":"The paper proposes a symbolic framework to address the binding problem for embedded VLIW ASIPs. Alternative objective functions as well as trade-offs relevant to the binding phase of code generation for embedded processors are presented and discussed. Experimental results obtained for a number of benchmarks extracted from the literature empirically demonstrate the promise of our approach.","PeriodicalId":437697,"journal":{"name":"Proceedings 2000 International Conference on Computer Design","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123280564","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Current-mode threshold logic gates 电流模式阈值逻辑门
Proceedings 2000 International Conference on Computer Design Pub Date : 2000-09-17 DOI: 10.1109/ICCD.2000.878291
S. Bobba, I. Hajj
{"title":"Current-mode threshold logic gates","authors":"S. Bobba, I. Hajj","doi":"10.1109/ICCD.2000.878291","DOIUrl":"https://doi.org/10.1109/ICCD.2000.878291","url":null,"abstract":"In this paper, we present low-power and high-performance logic gates called the current-mode threshold logic (CMTL) gates. Low-power dissipation is achieved by limiting the voltage swing on the interconnects and the internal nodes of the CMTL gates. High-performance is achieved by the use of transistor configurations that sense a small difference in current and set the differential outputs to the correct values. The realization of NAND, NOR, AND, OR logic gates and other logic functions using the CMTL gates is presented. We also present several implementations of CMTL gates and describe the relative advantages and limitations of these implementations. SPICE simulation, results for a 1.5 V 0.18 u CMOS technology are also presented for the different circuit configurations described in the paper.","PeriodicalId":437697,"journal":{"name":"Proceedings 2000 International Conference on Computer Design","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124724498","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
The 2-way thrashing-avoidance cache (TAC): an efficient instruction cache scheme for object-oriented languages 双向避免抖动缓存(TAC):面向对象语言的一种高效指令缓存方案
Proceedings 2000 International Conference on Computer Design Pub Date : 2000-09-17 DOI: 10.1109/ICCD.2000.878273
Y. Chu, M. Ito
{"title":"The 2-way thrashing-avoidance cache (TAC): an efficient instruction cache scheme for object-oriented languages","authors":"Y. Chu, M. Ito","doi":"10.1109/ICCD.2000.878273","DOIUrl":"https://doi.org/10.1109/ICCD.2000.878273","url":null,"abstract":"This paper presents a new instruction cache scheme: the TAC (Thrashing-Avoidance Cache). A 2-way TAC scheme employs 2-way banks and XOR mapping functions. The main function of the TAC is to place a group of instructions separated by a call instruction into a bank according to the Bank Selection Logic (BSL) and Bank-originated Pseudo-LRU replacement policies (BoPLRU). After the BSL initially selects a bank on an instruction cache miss, the BoPLRU will determine the final bank for updating a cache line as a correction mechanism. These two mechanisms can guarantee that recent groups of instructions exist in each bank safely. We have developed a simulation program, TACSim, by using Shade and Spixtools, provided by SUN Microsystems, on an ultra SPARC/10 processor. Our experimental results show that 2-way TAC schemes reduce conflict misses more effectively than 2-way skewed-associative caches in both C (17% improvement) and C++ (30% improvement) programs on L1 caches.","PeriodicalId":437697,"journal":{"name":"Proceedings 2000 International Conference on Computer Design","volume":"200 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122513091","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
On integrating a proprietary and a commercial architecture for optimal BIST performances in SoCs 在soc中集成专有和商业架构以获得最佳的BIST性能
Proceedings 2000 International Conference on Computer Design Pub Date : 2000-09-17 DOI: 10.1109/ICCD.2000.878335
A. Benso, S. Carlo, S. Chiusano, P. Prinetto, F. Ricciato, Monica Lobetti Bodoni, Maurizio Spadari
{"title":"On integrating a proprietary and a commercial architecture for optimal BIST performances in SoCs","authors":"A. Benso, S. Carlo, S. Chiusano, P. Prinetto, F. Ricciato, Monica Lobetti Bodoni, Maurizio Spadari","doi":"10.1109/ICCD.2000.878335","DOIUrl":"https://doi.org/10.1109/ICCD.2000.878335","url":null,"abstract":"This paper presents the integration of a proprietary hierarchical and distributed test access mechanism called HD/sup 2/BIST and a BIST insertion commercial tool. The paper briefly describes the architecture and the features of both the environments and it presents some experimental results obtained on an industrial SoC.","PeriodicalId":437697,"journal":{"name":"Proceedings 2000 International Conference on Computer Design","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125713958","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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