Proceedings 2000 International Conference on Computer Design最新文献_第3页

On test application time and defect detection capabilities of test sets for scan designs 扫描设计测试集的测试应用时间和缺陷检测能力

Proceedings 2000 International Conference on Computer Design Pub Date : 2000-09-17 DOI: 10.1109/ICCD.2000.878314

I. Pomeranz, S. Reddy

引用次数: 0

Architectural support for dynamic memory management 对动态内存管理的体系结构支持

Proceedings 2000 International Conference on Computer Design Pub Date : 2000-09-17 DOI: 10.1109/ICCD.2000.878274

J. M. Chang, W. Srisa-an, D. Lo

引用次数: 19

OpenDesign: an open user-configurable project environment for collaborative design and execution on the Internet OpenDesign:一个开放的用户可配置项目环境，用于互联网上的协同设计和执行

Proceedings 2000 International Conference on Computer Design Pub Date : 2000-09-17 DOI: 10.1109/ICCD.2000.878344

H. Lavana, F. Brglez, Robert B. Reese, Gangadhar Konduri, A. Chandrakasan

引用次数: 14

Formal verification of an industrial system-on-a-chip 一个工业系统芯片的正式验证

Proceedings 2000 International Conference on Computer Design Pub Date : 2000-09-17 DOI: 10.1109/ICCD.2000.878322

Hoon Choi, Myung-Kyoon Yim, Jae Young Lee, Byeong-Whee Yun, Yun-Tae Lee

引用次数: 6

Efficient dynamic minimization of word-level DDs based on lower bound computation 基于下界计算的字级dd的高效动态最小化

Proceedings 2000 International Conference on Computer Design Pub Date : 2000-09-17 DOI: 10.1109/ICCD.2000.878312

Wolfgang Günther, R. Drechsler, Stefan Höreth

引用次数: 3

Binary and multi-valued SPFD-based wire removal in PLA networks 基于二元和多值spfd的聚乳酸网络去线

Proceedings 2000 International Conference on Computer Design Pub Date : 2000-09-17 DOI: 10.1109/ICCD.2000.878328

Subarnarekha Sinha, S. Khatri, R. Brayton, A. Sangiovanni-Vincentelli

{"title":"Binary and multi-valued SPFD-based wire removal in PLA networks","authors":"Subarnarekha Sinha, S. Khatri, R. Brayton, A. Sangiovanni-Vincentelli","doi":"10.1109/ICCD.2000.878328","DOIUrl":"https://doi.org/10.1109/ICCD.2000.878328","url":null,"abstract":"This paper describes the application of binary and multivalued SPFD-based wire removal techniques for circuit implementations utilizing networks of PLAs. It has been shown that a design style based on a multi-level network of approximately equal-sized PLAs results in a dense, fast, and crosstalk-resistant layout. Wire removal is a technique where the total number of wires between individual circuit nodes is reduced, either by removing wires, or replacing them with other existing wires. Three separate wire removal experiments are performed. Either wire removal is invoked before clustering the original netlist into a network of PLAs, or after clustering, or both before and after clustering. For wire removal before clustering, binary SPFD-based wire removal is used. For wire removal after clustering, multi-valued SPFD-based wire removal is used since the multi-output PLAs can be viewed as multi-valued single output nodes. We demonstrate that these techniques are effective. The most effective approach is to perform wire removal both before and after clustering. Using these techniques, we obtain a reduction in placed and routed circuit area of about 11%. This reduction is significantly higher (about 20%) for the larger circuits we used in our experiments.","PeriodicalId":437697,"journal":{"name":"Proceedings 2000 International Conference on Computer Design","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128185279","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

A power perspective of value speculation for superscalar microprocessors 超标量微处理器价值推测的功率视角

Proceedings 2000 International Conference on Computer Design Pub Date : 2000-09-17 DOI: 10.1109/ICCD.2000.878281

R. Moreno, L. Piñuel, Silvia Del Pino, F. Tirado

引用次数: 15

A scalable high-performance DMA architecture for DSP applications 一个可扩展的高性能DMA架构，用于DSP应用

Proceedings 2000 International Conference on Computer Design Pub Date : 2000-09-17 DOI: 10.1109/ICCD.2000.878317

D. Comisky, S. Agarwala, Charles Fuoco

引用次数: 19

Multi-level communication synthesis of heterogeneous multilanguage specification 异构多语言规范的多级通信综合

Proceedings 2000 International Conference on Computer Design Pub Date : 2000-09-17 DOI: 10.1109/ICCD.2000.878332

Fabiano Hessel, P. Coste, G. Nicolescu, P. LeMarrec, N. Zergainoh, A. Jerraya

引用次数: 7

A multi-level memory system architecture for high performance DSP applications 一种用于高性能DSP应用的多级存储系统架构

Proceedings 2000 International Conference on Computer Design Pub Date : 2000-09-17 DOI: 10.1109/ICCD.2000.878316

S. Agarwala, Charles Fuoco, T. Anderson, D. Comisky, Christopher Mobley

{"title":"A multi-level memory system architecture for high performance DSP applications","authors":"S. Agarwala, Charles Fuoco, T. Anderson, D. Comisky, Christopher Mobley","doi":"10.1109/ICCD.2000.878316","DOIUrl":"https://doi.org/10.1109/ICCD.2000.878316","url":null,"abstract":"With the explosion of Digital Signal Processor (DSP) applications, there is a constant requirement for increased processing capability. This in turn requires rapid performance scaling in both operations per cycle and cycles per second, both of which result in increased MIPS/MMACS/MFLOPs. The memory system has to sustain the increased frequency and bandwidth demands in order to meet the data requirements of the DSP. Traditionally, DSP system architectures have on-chip addressable RAM, which is accessible by both the central processing unit (CPU) and the direct memory access (DMA). However, RAM frequencies are not scaling along with CPU clock rates, and as a result only relatively small RAM sizes are able to meet the frequency goals. This is in direct contrast to the increasing program size requirements seen by DSP applications, which in turn require even more on-chip RAM. This paper proposes a solution which has caches and RAMs coexisting in a homogeneous environment and working seamlessly together allowing high frequencies while still maintaining the DSP goals of low cost and low power. This multi-level memory system architecture has been implemented on the Texas Instruments (TI) TMS320C6211 C6x DSP.","PeriodicalId":437697,"journal":{"name":"Proceedings 2000 International Conference on Computer Design","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122746672","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10