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33rd International Symposium on Multiple-Valued Logic, 2003. Proceedings.最新文献

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Fuzzy logic as a basis for a theory of hierarchical definability (THD) 模糊逻辑作为层次可定义性理论的基础
33rd International Symposium on Multiple-Valued Logic, 2003. Proceedings. Pub Date : 2003-05-16 DOI: 10.1109/ISMVL.2003.1201375
L. Zadeh
{"title":"Fuzzy logic as a basis for a theory of hierarchical definability (THD)","authors":"L. Zadeh","doi":"10.1109/ISMVL.2003.1201375","DOIUrl":"https://doi.org/10.1109/ISMVL.2003.1201375","url":null,"abstract":"Attempts to formulate mathematically precise definitions of basic concepts such as causality, randomness and probability have a long history. The concept of hierarchical definability that is outlined in the following suggests that such definitions may not exist. Furthermore, it suggests that existing definitions of many basic concepts, among them those of linearity stability, statistical independence and Pareto-optimality, may be in need of reformulation.","PeriodicalId":434515,"journal":{"name":"33rd International Symposium on Multiple-Valued Logic, 2003. Proceedings.","volume":"133 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125441411","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Counter Tree Diagrams for design and analysis of fast addition algorithms 用于设计和分析快速加法算法的计数器树形图
33rd International Symposium on Multiple-Valued Logic, 2003. Proceedings. Pub Date : 2003-05-16 DOI: 10.1109/ISMVL.2003.1201390
Jun Sakiyama, T. Aoki, T. Higuchi
{"title":"Counter Tree Diagrams for design and analysis of fast addition algorithms","authors":"Jun Sakiyama, T. Aoki, T. Higuchi","doi":"10.1109/ISMVL.2003.1201390","DOIUrl":"https://doi.org/10.1109/ISMVL.2003.1201390","url":null,"abstract":"This paper presents a unified representation of fast addition algorithms based on Counter Tree Diagrams (CTDs). By using CTDs, we can describe and analyze various adder architectures in a systematic way without using specific knowledge about underlying arithmetic algorithms. Examples of adder architectures that can be handled by CTDs include Redundant-Binary (R-B) adders, Signed-Digit (SD) adders, Positive-Digit (PD) or carry-save adders, parallel counters (e.g., 3-2 counters and 4-2 counters) and networks of such basic adders/counters. This paper also discusses the CTD-based design and analysis of carry-propagation-free adders using redundant number representation.","PeriodicalId":434515,"journal":{"name":"33rd International Symposium on Multiple-Valued Logic, 2003. Proceedings.","volume":"108 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116778532","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Augmented sifting of multiple-valued decision diagrams 多值决策图的增强筛选
33rd International Symposium on Multiple-Valued Logic, 2003. Proceedings. Pub Date : 2003-05-16 DOI: 10.1109/ISMVL.2003.1201431
D. M. Miller, R. Drechsler
{"title":"Augmented sifting of multiple-valued decision diagrams","authors":"D. M. Miller, R. Drechsler","doi":"10.1109/ISMVL.2003.1201431","DOIUrl":"https://doi.org/10.1109/ISMVL.2003.1201431","url":null,"abstract":"Discrete functions are now commonly represented by binary (BDD) and multiple-valued (MDD) decision diagrams. Sifting is an effective heuristic technique which applies adjacent variable interchanges to find a good variable ordering to reduce the size of a BDD or MDD. Linear sifting is an extension of BDD sifting where XOR operations involving adjacent variable pairs augment adjacent variable interchange leading to further reduction in the node count. In this paper, we consider the extension of this approach to MDDs. In particular, we show that the XOR operation of linear sifting can be extended to a variety of operations. We term the resulting approach augmented sifting. Experimental results are presented showing sifting and augmented sifting can be quite effective in reducing the size of MDDs for certain types of functions.","PeriodicalId":434515,"journal":{"name":"33rd International Symposium on Multiple-Valued Logic, 2003. Proceedings.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130675102","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
The generation circulation method to generalized reed-muller coefficients over GF(3) GF(3)上广义reed-muller系数的生成循环法
33rd International Symposium on Multiple-Valued Logic, 2003. Proceedings. Pub Date : 2003-05-16 DOI: 10.1109/ISMVL.2003.1201383
Chol-U Lee, G. Byun, Bu-Sik Shin, Jae-Hwan Sim, Heung-Soo Kim
{"title":"The generation circulation method to generalized reed-muller coefficients over GF(3)","authors":"Chol-U Lee, G. Byun, Bu-Sik Shin, Jae-Hwan Sim, Heung-Soo Kim","doi":"10.1109/ISMVL.2003.1201383","DOIUrl":"https://doi.org/10.1109/ISMVL.2003.1201383","url":null,"abstract":"This paper propose the circulation method to generate GRM coefficient over GF(3). The general method to derive GRM coefficients are obtain RM expansion for the function and expand it for the polarities. The general method has many operations when the number of the variable is increased. Proposed method of this paper simplifies the generation process and reduces a number of operations compare to parallel type because of the cyclic property of polarity. To verify propriety of this method, previous proposed paper is compared in the number of operations.","PeriodicalId":434515,"journal":{"name":"33rd International Symposium on Multiple-Valued Logic, 2003. Proceedings.","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132680664","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Generalized complex spectral decision diagrams using unified complex Hadamard transform 统一复Hadamard变换的广义复谱决策图
33rd International Symposium on Multiple-Valued Logic, 2003. Proceedings. Pub Date : 2003-05-16 DOI: 10.1109/ISMVL.2003.1201433
S. Rahardja, S. Xie
{"title":"Generalized complex spectral decision diagrams using unified complex Hadamard transform","authors":"S. Rahardja, S. Xie","doi":"10.1109/ISMVL.2003.1201433","DOIUrl":"https://doi.org/10.1109/ISMVL.2003.1201433","url":null,"abstract":"This paper focuses on the study of different decision diagrams for representations of binary and multiple-valued functions using both the unified complex Hadamard transforms (UCHTs) whose transformation matrices contain elements /spl plusmn/1 and /spl plusmn/i and their Spectra. Types of the underlying decision diagrams are: hybrid decision diagrams, complex multi-terminal decision diagrams, complex algebraic decision diagrams, real and imaginary decision diagrams. Since UCHT unifies sixty-four different complex Hadamard transformation, it can provide a unified complex Hadamard spectral transform decision diagram. These more general complex Hadamard spectral decision diagrams generalize all results in [3, 4].","PeriodicalId":434515,"journal":{"name":"33rd International Symposium on Multiple-Valued Logic, 2003. Proceedings.","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129637715","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
MVL circuit design and characterization at the transistor level using SUS-LOC 使用SUS-LOC在晶体管级设计和表征MVL电路
33rd International Symposium on Multiple-Valued Logic, 2003. Proceedings. Pub Date : 2003-05-16 DOI: 10.1109/ISMVL.2003.1201392
E. Kinvi-Boh, M. Aline, O. Sentieys, E. D. Olson
{"title":"MVL circuit design and characterization at the transistor level using SUS-LOC","authors":"E. Kinvi-Boh, M. Aline, O. Sentieys, E. D. Olson","doi":"10.1109/ISMVL.2003.1201392","DOIUrl":"https://doi.org/10.1109/ISMVL.2003.1201392","url":null,"abstract":"This paper deals with design and performance estimation of typical ternary functions using SUS-LOC concepts. Experimental models of the transistors needed for SUS-LOC structures are presented. A created characterization process allows to extract the delay and the energy consumption information from each cell which is simulated at the transistor level. Finally, VHDL is used to obtain performances modelling and architectural-level simulation. Some characterization results are presented for basic logic ternary functions and a comparison between binary and ternary circuits is given for two adder structures.","PeriodicalId":434515,"journal":{"name":"33rd International Symposium on Multiple-Valued Logic, 2003. Proceedings.","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123239625","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
Using games for benchmarking and representing the complete solution space using symbolic techniques 使用游戏进行基准测试，并使用符号技术表示完整的解决方案空间
33rd International Symposium on Multiple-Valued Logic, 2003. Proceedings. Pub Date : 2003-05-16 DOI: 10.1109/ISMVL.2003.1201429
G. Fey, S. Kinder, R. Drechsler
{"title":"Using games for benchmarking and representing the complete solution space using symbolic techniques","authors":"G. Fey, S. Kinder, R. Drechsler","doi":"10.1109/ISMVL.2003.1201429","DOIUrl":"https://doi.org/10.1109/ISMVL.2003.1201429","url":null,"abstract":"Games often are inherently multi-valued problems and their wide variety offers different graduations of complexity. Moreover a lot of games have a parameter, like board-size that allows to generate differently sized instances of the same problem. All this makes them perfectly suitable for benchmarking in the multi-valued domain. So far the lack of benchmarks in this area often was compensated by transferring problems from binary to multi-valued, but for several application domains this is not adequate. This paper focuses on three games, that we consider suitable for benchmarking. We show the differences in complexity of the games and compare two coding schemes for one of them. All three problems are modeled by symbolic techniques, namely decision diagrams, leading to a complete representation of the solution space. This representation finds several applications, e.g. in objectively analyzing the efficiency of different heuristics on a solution space or to speed up learning algorithms.","PeriodicalId":434515,"journal":{"name":"33rd International Symposium on Multiple-Valued Logic, 2003. Proceedings.","volume":"113 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122908992","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Multi-output Galois Field Sum of Products synthesis with new quantum cascades 新型量子级联的多输出伽罗瓦场积和合成
33rd International Symposium on Multiple-Valued Logic, 2003. Proceedings. Pub Date : 2003-05-16 DOI: 10.1109/ISMVL.2003.1201399
Mozammel H. A. Khan, M. Perkowski, P. Kerntopf
{"title":"Multi-output Galois Field Sum of Products synthesis with new quantum cascades","authors":"Mozammel H. A. Khan, M. Perkowski, P. Kerntopf","doi":"10.1109/ISMVL.2003.1201399","DOIUrl":"https://doi.org/10.1109/ISMVL.2003.1201399","url":null,"abstract":"Galois Field Sum of Products (GFSOP) leads to efficient multi-valued reversible circuit synthesis using quantum gates. In this paper, we propose a new generalization of ternary Toffoli gate and another new generalized reversible ternary gale with discussion of their quantum realizations. Algorithms for synthesizing ternary GFSOP using quantum cascades of these gates are proposed In both the synthesis methods, 5 ternary shift operators and ternary swap gate are used We also propose quantum realizations of 5 ternary shift operators and ternary swap gate. In the cascades of the new ternary gates, local mirrors, variable ordering, and product ordering techniques are used to reduce the circuit cost. Experimental results show that the cascade of the new ternary gates is more efficient than the cascade of ternary Toffoli gates.","PeriodicalId":434515,"journal":{"name":"33rd International Symposium on Multiple-Valued Logic, 2003. Proceedings.","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116920627","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 67
Experimental and simulation studies of single-electron-transistor-based multiple-valued logic 基于单电子晶体管的多值逻辑的实验与仿真研究
33rd International Symposium on Multiple-Valued Logic, 2003. Proceedings. Pub Date : 2003-05-16 DOI: 10.1109/ISMVL.2003.1201415
H. Inokawa, Yasuo Takahashi
{"title":"Experimental and simulation studies of single-electron-transistor-based multiple-valued logic","authors":"H. Inokawa, Yasuo Takahashi","doi":"10.1109/ISMVL.2003.1201415","DOIUrl":"https://doi.org/10.1109/ISMVL.2003.1201415","url":null,"abstract":"Periodic drain current-gate voltage characteristics of single-electron transistors (SETs) were utilized to construct basic components of multiple-valued logic (MVL), such as a universal literal gate and a quantizer. In order to supplement the small gain and the small applicable voltage of the SET, hybrid SET-MOSFET scheme is proposed and demonstrated experimentally using CMOS-compatible pattern-dependent oxidation (PADOX) technology. We also succeeded in reproducing the results using a SPICE circuit simulator with a compact analytical SET model, and estimated the performance of the proposed MVL.","PeriodicalId":434515,"journal":{"name":"33rd International Symposium on Multiple-Valued Logic, 2003. Proceedings.","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133679714","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
Iterative symmetry indices decomposition for ternary logic synthesis in three-dimensional space 三维空间三元逻辑综合的迭代对称指标分解
33rd International Symposium on Multiple-Valued Logic, 2003. Proceedings. Pub Date : 2003-05-16 DOI: 10.1109/ISMVL.2003.1201398
A. Al-Rabadi
{"title":"Iterative symmetry indices decomposition for ternary logic synthesis in three-dimensional space","authors":"A. Al-Rabadi","doi":"10.1109/ISMVL.2003.1201398","DOIUrl":"https://doi.org/10.1109/ISMVL.2003.1201398","url":null,"abstract":"This paper introduces the implementation of the Iterative Symmetry Indices Decomposition (ISID) for the synthesis of ternary three-dimensional logic circuits. The synthesis of regular two-dimensional circuits using ISID has been introduced previously, and the synthesis of area-specific circuits using ISID has been demonstrated The new method is useful for the synthesis of functions using three-dimensional regular logic circuits whenever volume-specific layout constraints have to be satisfied.","PeriodicalId":434515,"journal":{"name":"33rd International Symposium on Multiple-Valued Logic, 2003. Proceedings.","volume":"30 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132502756","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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