Iterative symmetry indices decomposition for ternary logic synthesis in three-dimensional space

Abstract

This paper introduces the implementation of the Iterative Symmetry Indices Decomposition (ISID) for the synthesis of ternary three-dimensional logic circuits. The synthesis of regular two-dimensional circuits using ISID has been introduced previously, and the synthesis of area-specific circuits using ISID has been demonstrated The new method is useful for the synthesis of functions using three-dimensional regular logic circuits whenever volume-specific layout constraints have to be satisfied.