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33rd International Symposium on Multiple-Valued Logic, 2003. Proceedings.最新文献

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Fast algorithm for computing spectral transforms of Boolean and multiple-valued functions on circuit representation 基于电路表示的布尔函数和多值函数谱变换的快速计算算法
33rd International Symposium on Multiple-Valued Logic, 2003. Proceedings. Pub Date : 2003-05-16 DOI: 10.1109/ISMVL.2003.1201426
R. Krenz, E. Dubrova, A. Kuehlmann
{"title":"Fast algorithm for computing spectral transforms of Boolean and multiple-valued functions on circuit representation","authors":"R. Krenz, E. Dubrova, A. Kuehlmann","doi":"10.1109/ISMVL.2003.1201426","DOIUrl":"https://doi.org/10.1109/ISMVL.2003.1201426","url":null,"abstract":"In this paper we present a fast algorithm for computing the value of a spectral transform of Boolean or multiple-valued functions for a given assignment of input variables. Our current implementation is for arithmetic transform, because our work is primarily aimed at optimizing the performance of probabilistic verification methods. However, the presented technique is equally applicable for other discrete transforms, e.g. Walsh or Reed-Muller transforms. Previous methods for computing spectral transforms used truth tables, sum-of-product expressions, or various derivatives of decision diagrams. They were fundamentally limited by the excessive memory requirements of these data structures. We present a new algorithm that partitions the computation of the spectral transform based on the dominator relations of the circuit graph representing the function to be transformed. As a result, the presented algorithm can handle larger functions than previously possible.","PeriodicalId":434515,"journal":{"name":"33rd International Symposium on Multiple-Valued Logic, 2003. Proceedings.","volume":"104 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115716988","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Modeling multi-valued circuits in SystemC* 在SystemC*中建模多值电路
33rd International Symposium on Multiple-Valued Logic, 2003. Proceedings. Pub Date : 2003-05-16 DOI: 10.1109/ISMVL.2003.1201418
Daniel Große, G. Fey, R. Drechsler
{"title":"Modeling multi-valued circuits in SystemC*","authors":"Daniel Große, G. Fey, R. Drechsler","doi":"10.1109/ISMVL.2003.1201418","DOIUrl":"https://doi.org/10.1109/ISMVL.2003.1201418","url":null,"abstract":"The complexity of todays hardware systems steadily increases. Due to this fact new ways of efficiently describing systems are investigated. A very promising approach in this area is SystemC which is a C++-library. To take advantage of SystemC in the multi-valued domain, the concept of multi-valued logic has to be embedded in SystemC In this paper such a concept is introduced and details of the implementation are given. This creates a powerful development environment to model and efficiently simulate complex multi-valued circuits and systems. Due to C++-concepts, like operator overloading and templates, the task of modeling circuits becomes very convenient and handling of multi-valued signals is elegant. This gives the opportunity to design large circuits that can be mapped onto physically multi-valued gates. A scalable arithmetic logic unit is studied and experimental results are given.","PeriodicalId":434515,"journal":{"name":"33rd International Symposium on Multiple-Valued Logic, 2003. Proceedings.","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124619666","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Family of fast transforms over GF(3) logic GF(3)逻辑上的快速变换族
33rd International Symposium on Multiple-Valued Logic, 2003. Proceedings. Pub Date : 2003-05-16 DOI: 10.1109/ISMVL.2003.1201424
B. Falkowski, Cheng Fu
{"title":"Family of fast transforms over GF(3) logic","authors":"B. Falkowski, Cheng Fu","doi":"10.1109/ISMVL.2003.1201424","DOIUrl":"https://doi.org/10.1109/ISMVL.2003.1201424","url":null,"abstract":"New classes of recursive transforms over GF(3) have been introduced here. They are based on simple recursive equations what allows to obtain corresponding fast forward and inverse transforms and very regular butterfly diagrams. The classification is further extended into various transforms with horizontal and vertical permutations. The relations between various classes of introduced ternary transforms are also discussed.","PeriodicalId":434515,"journal":{"name":"33rd International Symposium on Multiple-Valued Logic, 2003. Proceedings.","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125319916","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
A novel technology mapping method for AND/XOR expressions 一种新的与/异或表达式的技术映射方法
33rd International Symposium on Multiple-Valued Logic, 2003. Proceedings. Pub Date : 2003-05-16 DOI: 10.1109/ISMVL.2003.1201397
S. Ko, Jien-Chung Lo
{"title":"A novel technology mapping method for AND/XOR expressions","authors":"S. Ko, Jien-Chung Lo","doi":"10.1109/ISMVL.2003.1201397","DOIUrl":"https://doi.org/10.1109/ISMVL.2003.1201397","url":null,"abstract":"In this paper we propose a novel technology mapping technique for Look-Up Table (LUT) - based Field Programmable Gate Arrays (FPGA). The proposed technology mapping technique is based on AND/exclusive-OR (XOR) expressions. The AND/XOR nature of the proposed techniques can map many important XOR-intensive applications, such as error detecting/correcting, data encryption/decryption, and computer arithmetic circuits efficiently in FPGA. The typical EDA tools deal mainly with AND/OR expressions and therefore are quite inefficient for XOR-intensive applications. We design a new approach and conduct experiments using MCNC benchmark circuits in FPGA environment to demonstrate the effectiveness of our proposed technology mapping technique. The proposed technique is superior to the typical methods with respect to area. When using the proposed technique, the number of CLB is reduced by 67.6% (speed-optimized one) and 57.7% (area-optimized one) and the total number of equivalent gate counts is also reduced by 65.5% compared to the typical methods.","PeriodicalId":434515,"journal":{"name":"33rd International Symposium on Multiple-Valued Logic, 2003. Proceedings.","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130254023","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
From intuitionistic logic to godel-dummett logic via parallel dialogue games 通过平行对话游戏从直觉逻辑到哥德-傻瓜逻辑
33rd International Symposium on Multiple-Valued Logic, 2003. Proceedings. Pub Date : 2003-05-16 DOI: 10.1109/ISMVL.2003.1201405
C. Fermüller, A. Ciabattoni
{"title":"From intuitionistic logic to godel-dummett logic via parallel dialogue games","authors":"C. Fermüller, A. Ciabattoni","doi":"10.1109/ISMVL.2003.1201405","DOIUrl":"https://doi.org/10.1109/ISMVL.2003.1201405","url":null,"abstract":"Building on a version of Lorenzen's dialogue foundation for intuitionistic logic, we show that Godel-Dummett logic G can be characterized by a suitable game of communicating parallel dialogues. This provides a computational interpretation of Avron's hypersequent calculus for G.","PeriodicalId":434515,"journal":{"name":"33rd International Symposium on Multiple-Valued Logic, 2003. Proceedings.","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122230362","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
Hyperoperations on {0, 1, 2} based on Min, Max, and Universal Literal operations 基于最小、最大和通用文字操作的{0,1,2}上的超操作
33rd International Symposium on Multiple-Valued Logic, 2003. Proceedings. Pub Date : 2003-05-16 DOI: 10.1109/ISMVL.2003.1201378
N. Takagi, K. Nakashima
{"title":"Hyperoperations on {0, 1, 2} based on Min, Max, and Universal Literal operations","authors":"N. Takagi, K. Nakashima","doi":"10.1109/ISMVL.2003.1201378","DOIUrl":"https://doi.org/10.1109/ISMVL.2003.1201378","url":null,"abstract":"This paper will discuss functions with hyperstructure based on Min, Max, and Universal Literal operations on {0, 1, 2}. These three types of operations will be expanded into operations on the set P/sub 3/ of non-empty subsets of {0, 1, 2}. Then, the paper will define a special type of compositions, called formulas, and will show a necessary and sufficient condition for a function on P/sub 3/ to be expressed by a formula.","PeriodicalId":434515,"journal":{"name":"33rd International Symposium on Multiple-Valued Logic, 2003. Proceedings.","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127657920","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Complementary self-biased scheme for the robust design of CMOS/SET hybrid multi-valued logic CMOS/SET混合多值逻辑鲁棒设计的互补自偏置方案
33rd International Symposium on Multiple-Valued Logic, 2003. Proceedings. Pub Date : 2003-05-16 DOI: 10.1109/ISMVL.2003.1201416
Ki-Whan Song, Sang-Hoon Lee, D. Kim, K. Kim, J. Kyung, Gwang-Hyun Baek, C. Lee, J. Lee, Byung-Gook Park
{"title":"Complementary self-biased scheme for the robust design of CMOS/SET hybrid multi-valued logic","authors":"Ki-Whan Song, Sang-Hoon Lee, D. Kim, K. Kim, J. Kyung, Gwang-Hyun Baek, C. Lee, J. Lee, Byung-Gook Park","doi":"10.1109/ISMVL.2003.1201416","DOIUrl":"https://doi.org/10.1109/ISMVL.2003.1201416","url":null,"abstract":"We propose a new technique to enhance the characteristics of CMOS/SET hybrid multi-valued logic (MVL) circuits in terms of their stability and performance. A complementary self-biasing method enables the SET/CMOS logic to operate perfectly well at high temperature in which the peak-to-valley current ratio of Coulomb oscillation severely decreases. The suggested scheme is evaluated by SPICE simulation with an analytical SET model, and it is confirmed that even SETs with a large Si island can be utilized efficiently in the multi-valued logic. We demonstrate a quantizer implemented by SETs with a 90-nm-long Si island on the basis of measured device characteristics and SPICE simulation, which shows high resolution and small linearity error characteristics.","PeriodicalId":434515,"journal":{"name":"33rd International Symposium on Multiple-Valued Logic, 2003. Proceedings.","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133129925","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Generation of the Post Lattice by irreducible clones 不可约克隆后格的生成
33rd International Symposium on Multiple-Valued Logic, 2003. Proceedings. Pub Date : 2003-05-16 DOI: 10.1109/ISMVL.2003.1201422
Grant R. Pogosyan, I. Rosenberg
{"title":"Generation of the Post Lattice by irreducible clones","authors":"Grant R. Pogosyan, I. Rosenberg","doi":"10.1109/ISMVL.2003.1201422","DOIUrl":"https://doi.org/10.1109/ISMVL.2003.1201422","url":null,"abstract":"Clones of logic functions form an algebraic lattice, which in the case of Boolean functions was completely described by E.L.Post in 1941. This lattice, often referred to as the Post Lattice, has been well studied from various angles, particularly, the generation of the Post Lattice by its subsets. This paper discusses the results about clones that are irreducible by means of meet- and/or join-operations of the lattice. We show that the join-irreducible clones generate the Post Lattice, and dually, the meet-irreducible clones generate the Post Lattice. We present a complete description of such generation in both cases. We observe that any clone can be presented as a join or meet of at most two irreducible clones. In the former case each clone is the join of at most four join-irreducible clones and in the latter case each clone is the meet of at most three meet-irreducible ones.","PeriodicalId":434515,"journal":{"name":"33rd International Symposium on Multiple-Valued Logic, 2003. Proceedings.","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131322299","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Compact representations of logic functions using heterogeneous MDDs 使用异构mdd的逻辑函数的紧凑表示
33rd International Symposium on Multiple-Valued Logic, 2003. Proceedings. Pub Date : 2003-05-16 DOI: 10.1109/ISMVL.2003.1201413
Shinobu Nagayama, Tsutomu Sasao
{"title":"Compact representations of logic functions using heterogeneous MDDs","authors":"Shinobu Nagayama, Tsutomu Sasao","doi":"10.1109/ISMVL.2003.1201413","DOIUrl":"https://doi.org/10.1109/ISMVL.2003.1201413","url":null,"abstract":"In this paper we propose a compact representation of logic functions using Multi-valued Decision Diagrams (MDDs) called heterogeneous MDDs. In a heterogeneous MDD, each variable may take a different domain. By partitioning binary input variables and representing each partition as a single multi-valued variable, we can produce a heterogeneous MDD with 16% smaller memory size than a Reduced Ordered Binary Decision Diagram (ROBDD), and with as small memory size as the Free Binary Decision Diagrams (FBDDs). We minimized a large number of benchmark functions to show the compactness of heterogeneous MDDs.","PeriodicalId":434515,"journal":{"name":"33rd International Symposium on Multiple-Valued Logic, 2003. Proceedings.","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114709669","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 44
An extension of ternary majority function and its application to evolvable system 三元多数函数的扩展及其在可演化系统中的应用
33rd International Symposium on Multiple-Valued Logic, 2003. Proceedings. Pub Date : 2003-05-16 DOI: 10.1109/ISMVL.2003.1201379
Yoshinori Yamamoto
{"title":"An extension of ternary majority function and its application to evolvable system","authors":"Yoshinori Yamamoto","doi":"10.1109/ISMVL.2003.1201379","DOIUrl":"https://doi.org/10.1109/ISMVL.2003.1201379","url":null,"abstract":"Multiple-valued majority functions were defined in 1980 as a group which differ from; threshold functions, but the majority functions only consist of a subset of Kleenean functions. This paper defines an extension of the ternary majority function using cyclic operation to I/O values of the function. The extended ternary majority functions are functionally complete on a ternary logic system. We apply this function to synsthesize evolvable logic system. The goal of the discussion in the latter half is to devise a method of representing any ternary logic function using the extended ternary majority functions. GA is used as a tool, and an advanced method applicable to many variable case is proposed together with some experiments.","PeriodicalId":434515,"journal":{"name":"33rd International Symposium on Multiple-Valued Logic, 2003. Proceedings.","volume":"790 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120932591","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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