Complementary self-biased scheme for the robust design of CMOS/SET hybrid multi-valued logic

Abstract

We propose a new technique to enhance the characteristics of CMOS/SET hybrid multi-valued logic (MVL) circuits in terms of their stability and performance. A complementary self-biasing method enables the SET/CMOS logic to operate perfectly well at high temperature in which the peak-to-valley current ratio of Coulomb oscillation severely decreases. The suggested scheme is evaluated by SPICE simulation with an analytical SET model, and it is confirmed that even SETs with a large Si island can be utilized efficiently in the multi-valued logic. We demonstrate a quantizer implemented by SETs with a 90-nm-long Si island on the basis of measured device characteristics and SPICE simulation, which shows high resolution and small linearity error characteristics.