Proceedings 14th IEEE Symposium on Computer Arithmetic (Cat. No.99CB36336)最新文献_第2页

On the design of high-radix on-line division for long precision 长精度高基数在线除法的设计

Proceedings 14th IEEE Symposium on Computer Arithmetic (Cat. No.99CB36336) Pub Date : 1999-04-14 DOI: 10.1109/ARITH.1999.762827

A. Tenca, M. Ercegovac

引用次数: 8

A 32 bit logarithmic arithmetic unit and its performance compared to floating-point 一种32位对数运算单元及其与浮点数的性能比较

Proceedings 14th IEEE Symposium on Computer Arithmetic (Cat. No.99CB36336) Pub Date : 1999-04-14 DOI: 10.1109/ARITH.1999.762839

J. N. Coleman, E. Chester

引用次数: 50

Floating-point unit in standard cell design with 116 bit wide dataflow 标准单元设计中的浮点单元，具有116位宽的数据流

Proceedings 14th IEEE Symposium on Computer Arithmetic (Cat. No.99CB36336) Pub Date : 1999-04-14 DOI: 10.1109/ARITH.1999.762853

Guenter Gerwig, M. Kroener

引用次数: 23

Low-power division: comparison among implementations of radix 4, 8 and 16 低功耗除法:基数4,8和16的实现比较

Proceedings 14th IEEE Symposium on Computer Arithmetic (Cat. No.99CB36336) Pub Date : 1999-04-14 DOI: 10.1109/ARITH.1999.762829

A. Nannarelli, T. Lang

引用次数: 15

VLSI costs of arithmetic parallelism: a residue reverse conversion perspective VLSI的算术并行开销:一个残数反向转换的观点

Proceedings 14th IEEE Symposium on Computer Arithmetic (Cat. No.99CB36336) Pub Date : 1999-04-14 DOI: 10.1109/ARITH.1999.762843

M. Bhardwaj, T. Srikanthan, C. Clarke

引用次数: 8

Area/spl times/delay (A/spl middot/T) efficient multiplier based on an intermediate hybrid signed-digit (HSD-1) representation 基于中间混合符号数字(HSD-1)表示的面积/spl时间/延迟(A/spl中点/T)高效乘法器

Proceedings 14th IEEE Symposium on Computer Arithmetic (Cat. No.99CB36336) Pub Date : 1999-04-14 DOI: 10.1109/ARITH.1999.762847

Jeng-Jong J. Lue, D. Phatak

{"title":"Area/spl times/delay (A/spl middot/T) efficient multiplier based on an intermediate hybrid signed-digit (HSD-1) representation","authors":"Jeng-Jong J. Lue, D. Phatak","doi":"10.1109/ARITH.1999.762847","DOIUrl":"https://doi.org/10.1109/ARITH.1999.762847","url":null,"abstract":"Intermediate Signed Digit (SD) representation can facilitate fast and compact VLSI implementations of partial product accumulation trees. It achieves a reduction ratio of 2:1 at every level and also leads to more regular layouts. Its disadvantage is that the number of bit lines that need to be routed can be high. This can lead to a significant area overhead especially at smaller feature sizes where the wire/interconnect area and delay can be dominant. A Hybrid Signed Digit (HSD) representation lets some of the digits be unsigned bits, thereby reducing the number of bit lines. By arbitrarily varying the positions of and distances between consecutive signed digits, this representation can trade off latency for area and offers a continuum of choices between the two's complement representation on the one hand and fully Signed Digit (FSD or simply SD) representation on the other. We illustrate an A/spl middot/T (area/spl times/delay) efficient multiplier based on the HSD-1 representation which is one of the many possible HSD formats, wherein every alternate digit is signed and the rest are unsigned (ordinary) bits. It is seen that multipliers based on HSD-1 format require more transistors than those based on FSD format. However, they require fewer bit lines to be routed, which substantially reduces the interconnect area; thereby leading to a reduction in the total VLSI area and a lower A/spl middot/T product. The design reaffirms that the interconnect area can be significant, especially at small feature sizes.","PeriodicalId":434169,"journal":{"name":"Proceedings 14th IEEE Symposium on Computer Arithmetic (Cat. No.99CB36336)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132390589","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Intermediate variable encodings that enable multiplexor-based implementations of two operand addition 中间变量编码，支持基于多路器的两个操作数加法实现

Proceedings 14th IEEE Symposium on Computer Arithmetic (Cat. No.99CB36336) Pub Date : 1999-04-14 DOI: 10.1109/ARITH.1999.762824

D. Phatak, I. Koren

引用次数: 5

Reduced latency IEEE floating-point standard adder architectures 降低延迟IEEE浮点标准加法器架构

Proceedings 14th IEEE Symposium on Computer Arithmetic (Cat. No.99CB36336) Pub Date : 1999-04-14 DOI: 10.1109/ARITH.1999.762826

A. Beaumont-Smith, N. Burgess, S. Lefrere, C. Lim

引用次数: 69

Montgomery modular exponentiation on reconfigurable hardware 可重构硬件上的Montgomery模幂运算

Proceedings 14th IEEE Symposium on Computer Arithmetic (Cat. No.99CB36336) Pub Date : 1999-04-14 DOI: 10.1109/ARITH.1999.762831

Thomas Blum

{"title":"Montgomery modular exponentiation on reconfigurable hardware","authors":"Thomas Blum","doi":"10.1109/ARITH.1999.762831","DOIUrl":"https://doi.org/10.1109/ARITH.1999.762831","url":null,"abstract":"It is widely recognized that security issues will play a crucial role in the majority of future computer and communication systems. Central tools for achieving system security are cryptographic algorithms. For performance as well as for physical security reasons, it is often advantageous to realize cryptographic algorithms in hardware. In order to overcome the well-known drawback of reduced flexibility that is associated with traditional ASIC solutions, this contribution proposes arithmetic architectures which are optimized for modern field programmable gate arrays (FPGAs). The proposed architectures perform modular exponentiation with very long integers. This operation is at the heart of many practical public-key algorithms such as RSA and discrete logarithm schemes. We combine the Montgomery modular multiplication algorithm with a new systolic array design, which is capable of processing a variable number of bits per array cell. The designs are flexible, allowing any choice of operand and modulus. Unlike previous approaches, we systematically implement and compare several variants of our new architecture for different bit lengths. We provide absolute area and timing measures for each architecture. The results allow conclusions about the feasibility and time-space trade-offs of our architecture for implementation on Xilinx XC4000 series FPGAs. As a major practical result we show that it is possible to implement modular exponentiation at secure bit lengths on a single commercially available FPGA.","PeriodicalId":434169,"journal":{"name":"Proceedings 14th IEEE Symposium on Computer Arithmetic (Cat. No.99CB36336)","volume":"37 7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125733835","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 206

Complex logarithmic number system arithmetic using high-radix redundant CORDIC algorithms 使用高基数冗余CORDIC算法的复对数系统算术

Proceedings 14th IEEE Symposium on Computer Arithmetic (Cat. No.99CB36336) Pub Date : 1999-04-14 DOI: 10.1109/ARITH.1999.762845

D. Lewis

引用次数: 24