{"title":"降低延迟IEEE浮点标准加法器架构","authors":"A. Beaumont-Smith, N. Burgess, S. Lefrere, C. Lim","doi":"10.1109/ARITH.1999.762826","DOIUrl":null,"url":null,"abstract":"The design and implementation of a double precision floating-point IEEE-754 standard adder is described which uses \"flagged prefix addition\" to merge rounding with the significand addition. The floating-point adder is implemented in 0.5 /spl mu/m CMOS, measures 1.8 mm/sup 2/, has a 3-cycle latency and implements all rounding modes. A modified version of this floating-point adder can perform accumulation in 2-cycles with a small amount of extra hardware for use in a parallel processor node. This is achieved by feeding back the previous un-normalised but correctly rounded result together with the normalisation distance. A 2-cycle latency floating-point adder architecture with potentially the same cycle time that also employs flagged prefix addition is described. It also incorporates a fast prediction scheme for the true subtraction of significands with an exponent difference of 1, with one less adder.","PeriodicalId":434169,"journal":{"name":"Proceedings 14th IEEE Symposium on Computer Arithmetic (Cat. No.99CB36336)","volume":"78 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1999-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"69","resultStr":"{\"title\":\"Reduced latency IEEE floating-point standard adder architectures\",\"authors\":\"A. Beaumont-Smith, N. Burgess, S. Lefrere, C. Lim\",\"doi\":\"10.1109/ARITH.1999.762826\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The design and implementation of a double precision floating-point IEEE-754 standard adder is described which uses \\\"flagged prefix addition\\\" to merge rounding with the significand addition. The floating-point adder is implemented in 0.5 /spl mu/m CMOS, measures 1.8 mm/sup 2/, has a 3-cycle latency and implements all rounding modes. A modified version of this floating-point adder can perform accumulation in 2-cycles with a small amount of extra hardware for use in a parallel processor node. This is achieved by feeding back the previous un-normalised but correctly rounded result together with the normalisation distance. A 2-cycle latency floating-point adder architecture with potentially the same cycle time that also employs flagged prefix addition is described. It also incorporates a fast prediction scheme for the true subtraction of significands with an exponent difference of 1, with one less adder.\",\"PeriodicalId\":434169,\"journal\":{\"name\":\"Proceedings 14th IEEE Symposium on Computer Arithmetic (Cat. No.99CB36336)\",\"volume\":\"78 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1999-04-14\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"69\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings 14th IEEE Symposium on Computer Arithmetic (Cat. No.99CB36336)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ARITH.1999.762826\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings 14th IEEE Symposium on Computer Arithmetic (Cat. No.99CB36336)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ARITH.1999.762826","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Reduced latency IEEE floating-point standard adder architectures
The design and implementation of a double precision floating-point IEEE-754 standard adder is described which uses "flagged prefix addition" to merge rounding with the significand addition. The floating-point adder is implemented in 0.5 /spl mu/m CMOS, measures 1.8 mm/sup 2/, has a 3-cycle latency and implements all rounding modes. A modified version of this floating-point adder can perform accumulation in 2-cycles with a small amount of extra hardware for use in a parallel processor node. This is achieved by feeding back the previous un-normalised but correctly rounded result together with the normalisation distance. A 2-cycle latency floating-point adder architecture with potentially the same cycle time that also employs flagged prefix addition is described. It also incorporates a fast prediction scheme for the true subtraction of significands with an exponent difference of 1, with one less adder.