Proceedings 14th IEEE Symposium on Computer Arithmetic (Cat. No.99CB36336)最新文献

A reverse converter for the 4-moduli superset {2/sup n/-1, 2/sup n/, 2/sup n/+1, 2/sup n+1/+1} 四模超集{2/sup n/- 1,2 /sup n/， 2/sup n/+ 1,2 /sup n+1/+1}的反向变换器

Proceedings 14th IEEE Symposium on Computer Arithmetic (Cat. No.99CB36336) Pub Date : 1999-04-14 DOI: 10.1109/ARITH.1999.762842

M. Bhardwaj, T. Srikanthan, C. Clarke

{"title":"A reverse converter for the 4-moduli superset {2/sup n/-1, 2/sup n/, 2/sup n/+1, 2/sup n+1/+1}","authors":"M. Bhardwaj, T. Srikanthan, C. Clarke","doi":"10.1109/ARITH.1999.762842","DOIUrl":"https://doi.org/10.1109/ARITH.1999.762842","url":null,"abstract":"The authors propose an extension to the popular {2/sup n/-1, 2/sup n/, 2/sup n/+1} moduli set by adding a fourth modulus \"2/sup n+1/+1. This extension leads to higher parallelism while keeping the forward conversion and modular arithmetic units simple. The main challenge of efficient reverse conversion is met by three techniques described for the first time. Firstly, we reverse convert linear combinations of moduli hence reducing the number of non-zero bits in the Booth encoded multiplicands from n to merely 2. Secondly, it is shown that division by 3, if introduced at the right stage, can be implemented very efficiently and can, in turn, reduce the cost of the converter. To implement VLSI efficient modulo reduction, we propose two techniques-multiple split tables (MST) and a modified division algorithm (MDA). It is shown that the MST can reduce exponential ROM requirements to quadratic ROM requirements while the MDA can reduce these further to linear requirements. As a result of these innovations, the proposed reverse converter uses simple shift and add operations and needs a lookup with only 6 entries. The delay of the converter is approximately 10n+13 full adder delays and the area cost is quadratic in n.","PeriodicalId":434169,"journal":{"name":"Proceedings 14th IEEE Symposium on Computer Arithmetic (Cat. No.99CB36336)","volume":"53 23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124650470","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 47

Correctness proofs outline for Newton-Raphson based floating-point divide and square root algorithms 基于牛顿-拉夫森浮点除法和平方根算法的正确性证明大纲

Proceedings 14th IEEE Symposium on Computer Arithmetic (Cat. No.99CB36336) Pub Date : 1999-04-14 DOI: 10.1109/ARITH.1999.762834

Marius A. Cornea-Hasegan, Roger A. Golliver, Peter W. Markstein

{"title":"Correctness proofs outline for Newton-Raphson based floating-point divide and square root algorithms","authors":"Marius A. Cornea-Hasegan, Roger A. Golliver, Peter W. Markstein","doi":"10.1109/ARITH.1999.762834","DOIUrl":"https://doi.org/10.1109/ARITH.1999.762834","url":null,"abstract":"This paper describes a study of a class of algorithms for the floating-point divide and square root operations, based on the Newton-Raphson iterative method. The two main goals were. (1) Proving the IEEE correctness of these iterative floating-point algorithms, i.e. compliance with the IEEE-754 standard for binary floating-point operations. The focus was on software driven iterative algorithms, instead of the hardware based implementations that dominated until now. (2) Identifying the special cases of operands that require results. Assistance due to possible overflow, or loss of precision of intermediate This study was initiated in an attempt to prove the IEEE for a class of divide and square root based on the Newton-Rapshson iterative methods. As more insight into the inner workings of these algorithms was gained, it became obvious that a formal study and proof were necessary in order to achieve the desired objectives. The result is a complete and rigorous proof of IEEE correctness for floating-point divide and square root algorithms based on the Newton-Raphson iterative method. Even more, the method used in proving the IEEE correctness of the square root algorithm is applicable in principle to any iterative algorithm, not only based on the Newton-Raphson method. Conditions requiring Software Assistance (SWA) were also determined, and were used to identify cases when alternate algorithms are needed to generate correct results. Overall, this is one important step toward flawless implementation of these floating-point operations based on software implementations.","PeriodicalId":434169,"journal":{"name":"Proceedings 14th IEEE Symposium on Computer Arithmetic (Cat. No.99CB36336)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128125680","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 62

On infinitely precise rounding for division, square root, reciprocal and square root reciprocal 关于除法、平方根、倒数和平方根倒数的无限精确舍入

Proceedings 14th IEEE Symposium on Computer Arithmetic (Cat. No.99CB36336) Pub Date : 1999-04-14 DOI: 10.1109/ARITH.1999.762849

Cristina Iordache, D. Matula

{"title":"On infinitely precise rounding for division, square root, reciprocal and square root reciprocal","authors":"Cristina Iordache, D. Matula","doi":"10.1109/ARITH.1999.762849","DOIUrl":"https://doi.org/10.1109/ARITH.1999.762849","url":null,"abstract":"Quotients, reciprocals, square roots and square root reciprocals all have the property that infinitely precise p-bit rounded results for p-bit input operands can be obtained from approximate results of bounded accuracy. We investigate lower bounds on the number of bits of an approximation accurate to a unit in the last place sufficient to guarantee that correct round and sticky bits can be determined. Known lower bounds for quotients and square roots are given and/or sharpened, and a new lower bound for root reciprocals is proved. Specifically for reciprocals, quotients and square roots, tight bounds of order 2p+O(1) are presented. For infinitely precise rounding of the root reciprocal, a lower bound can be found at 3p+O(1), but exhaustive testing for small sizes of the operand suggests that in practice (2+/spl epsiv/)p for small /spl epsiv/ is usually sufficient. Algorithms can be designed for obtaining the round and sticky bits based on the bit pattern of an approximation computed to the required accuracy. We show that some improvement of the known lower bound for reciprocals and division is achievable at the cost of somewhat more complex hardware for rounding. Tests for the exactness of the quotient and square root are also provided.","PeriodicalId":434169,"journal":{"name":"Proceedings 14th IEEE Symposium on Computer Arithmetic (Cat. No.99CB36336)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132284458","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 41

Series approximation methods for divide and square root in the Power3/sup TM/ processor Power3/sup TM/处理器中除法和平方根的级数逼近方法

Proceedings 14th IEEE Symposium on Computer Arithmetic (Cat. No.99CB36336) Pub Date : 1999-04-14 DOI: 10.1109/ARITH.1999.762836

M. Schmookler, R. Agarwal, F. Gustavson

引用次数: 29

Digit-recurrence algorithm for computing Euclidean norm of a 3-D vector 计算三维矢量欧几里得范数的数字递归算法

Proceedings 14th IEEE Symposium on Computer Arithmetic (Cat. No.99CB36336) Pub Date : 1999-04-14 DOI: 10.1109/ARITH.1999.762833

N. Takagi, S. Kuwahara

引用次数: 4

Interval sine and cosine functions computation based on variable-precision CORDIC algorithm 基于变精度CORDIC算法的区间正弦余弦函数计算

Proceedings 14th IEEE Symposium on Computer Arithmetic (Cat. No.99CB36336) Pub Date : 1999-04-14 DOI: 10.1109/ARITH.1999.762844

J. Hormigo, J. Villalba, E. Zapata

引用次数: 9

Number-theoretic test generation for directed rounding 有向舍入的数论测试生成

Proceedings 14th IEEE Symposium on Computer Arithmetic (Cat. No.99CB36336) Pub Date : 1999-04-14 DOI: 10.1109/ARITH.1999.762850

Michael Parks

引用次数: 37

High-speed inverse square roots 高速反平方根

Proceedings 14th IEEE Symposium on Computer Arithmetic (Cat. No.99CB36336) Pub Date : 1999-04-14 DOI: 10.1109/ARITH.1999.762837

M. Schulte, K. Wires

引用次数: 28

Moduli for testing implementations of the RSA cryptosystem 模用于测试RSA密码系统的实现

Proceedings 14th IEEE Symposium on Computer Arithmetic (Cat. No.99CB36336) Pub Date : 1999-04-14 DOI: 10.1109/ARITH.1999.762832

C. D. Walter

引用次数: 4

A low-power, high-speed implementation of a PowerPC/sup TM/ microprocessor vector extension 一个低功耗，高速实现的PowerPC/sup TM/微处理器矢量扩展

Proceedings 14th IEEE Symposium on Computer Arithmetic (Cat. No.99CB36336) Pub Date : 1999-04-14 DOI: 10.1109/ARITH.1999.762823

M. Schmookler, M. Putrino, Anh Mather, J. Tyler, Huy Nguyen, C. Roth, Mukesh Sharma, M. Pham, Jeff Lent

引用次数: 44