四模超集{2/sup n/- 1,2 /sup n/, 2/sup n/+ 1,2 /sup n+1/+1}的反向变换器

M. Bhardwaj, T. Srikanthan, C. Clarke
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引用次数: 47

摘要

本文通过增加一个第四模“2/sup n+1/+1”,对已有的{2/sup n/- 1,2 /sup n/, 2/sup n/+1}模集进行了扩展。这个扩展带来了更高的并行性,同时保持了前向转换和模块化算术单元的简单性。有效的反向转换的主要挑战是由三种技术首次描述。首先,我们对模的线性组合进行反向转换,从而将Booth编码乘数中的非零位数从n减少到仅仅2。其次,如果在正确的阶段引入除以3,可以非常有效地实施,从而可以降低转换器的成本。为了实现VLSI的高效降模,我们提出了两种技术-多分割表(MST)和改进的除法算法(MDA)。结果表明,MST可以将指数ROM需求降低到二次ROM需求,而MDA可以进一步降低到线性需求。由于这些创新,所建议的反向转换器使用简单的移位和添加操作,并且只需要6个条目的查找。转换器的延迟约为10n+13个全加法器延迟,面积代价为n的二次元。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A reverse converter for the 4-moduli superset {2/sup n/-1, 2/sup n/, 2/sup n/+1, 2/sup n+1/+1}
The authors propose an extension to the popular {2/sup n/-1, 2/sup n/, 2/sup n/+1} moduli set by adding a fourth modulus "2/sup n+1/+1. This extension leads to higher parallelism while keeping the forward conversion and modular arithmetic units simple. The main challenge of efficient reverse conversion is met by three techniques described for the first time. Firstly, we reverse convert linear combinations of moduli hence reducing the number of non-zero bits in the Booth encoded multiplicands from n to merely 2. Secondly, it is shown that division by 3, if introduced at the right stage, can be implemented very efficiently and can, in turn, reduce the cost of the converter. To implement VLSI efficient modulo reduction, we propose two techniques-multiple split tables (MST) and a modified division algorithm (MDA). It is shown that the MST can reduce exponential ROM requirements to quadratic ROM requirements while the MDA can reduce these further to linear requirements. As a result of these innovations, the proposed reverse converter uses simple shift and add operations and needs a lookup with only 6 entries. The delay of the converter is approximately 10n+13 full adder delays and the area cost is quadratic in n.
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