Reduced latency IEEE floating-point standard adder architectures

A. Beaumont-Smith, N. Burgess, S. Lefrere, C. Lim
{"title":"Reduced latency IEEE floating-point standard adder architectures","authors":"A. Beaumont-Smith, N. Burgess, S. Lefrere, C. Lim","doi":"10.1109/ARITH.1999.762826","DOIUrl":null,"url":null,"abstract":"The design and implementation of a double precision floating-point IEEE-754 standard adder is described which uses \"flagged prefix addition\" to merge rounding with the significand addition. The floating-point adder is implemented in 0.5 /spl mu/m CMOS, measures 1.8 mm/sup 2/, has a 3-cycle latency and implements all rounding modes. A modified version of this floating-point adder can perform accumulation in 2-cycles with a small amount of extra hardware for use in a parallel processor node. This is achieved by feeding back the previous un-normalised but correctly rounded result together with the normalisation distance. A 2-cycle latency floating-point adder architecture with potentially the same cycle time that also employs flagged prefix addition is described. It also incorporates a fast prediction scheme for the true subtraction of significands with an exponent difference of 1, with one less adder.","PeriodicalId":434169,"journal":{"name":"Proceedings 14th IEEE Symposium on Computer Arithmetic (Cat. No.99CB36336)","volume":"78 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1999-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"69","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings 14th IEEE Symposium on Computer Arithmetic (Cat. No.99CB36336)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ARITH.1999.762826","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 69

Abstract

The design and implementation of a double precision floating-point IEEE-754 standard adder is described which uses "flagged prefix addition" to merge rounding with the significand addition. The floating-point adder is implemented in 0.5 /spl mu/m CMOS, measures 1.8 mm/sup 2/, has a 3-cycle latency and implements all rounding modes. A modified version of this floating-point adder can perform accumulation in 2-cycles with a small amount of extra hardware for use in a parallel processor node. This is achieved by feeding back the previous un-normalised but correctly rounded result together with the normalisation distance. A 2-cycle latency floating-point adder architecture with potentially the same cycle time that also employs flagged prefix addition is described. It also incorporates a fast prediction scheme for the true subtraction of significands with an exponent difference of 1, with one less adder.
降低延迟IEEE浮点标准加法器架构
介绍了一种双精度浮点IEEE-754标准加法器的设计与实现,该加法器采用“标记前缀加法”将舍入与有效加法合并。该浮点加法器采用0.5 /spl mu/m CMOS,测量1.8 mm/sup /,具有3周期延迟并实现所有舍入模式。这个浮点加法器的修改版本可以在2个周期内完成累加,只需要在并行处理器节点中使用少量额外的硬件。这是通过将之前未规范化但正确舍入的结果与规范化距离一起反馈来实现的。本文描述了一种2周期延迟浮点加法器架构,其周期时间可能相同,但也采用了标记前缀加法。它还结合了一个快速预测方案,用于指数差为1的有效减法,加法器少一个。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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