长精度高基数在线除法的设计

A. Tenca, M. Ercegovac
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引用次数: 8

摘要

提出了一种适合于长精度计算的高基数在线除法的设计。该方案使用基于剩余四舍五入和操作数缩放的商位选择函数。根据全加法器延迟,得到了基数2/sup k/和n位精度下的循环数和周期时间的界限。对于k/spl ges/6和n/spl ges/64,相对于基数2的加速大于3.3。代价随着基数的增加而增加。对于r=64和n=64的情况,相对于r=2,面积的增加大约是6.6倍加上512/spl次/10位表。采用VHDL和MOSIS库中的1.2 /spl mu/m CMOS标准栅极技术对该方案进行了设计和验证。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
On the design of high-radix on-line division for long precision
We present a design of a high-radix on-line division suitable for long precision computations. The proposed scheme uses a quotient-digit selection function based on the residual rounding and scaling of the operands. The bounds on the number of cycles and the cycle time for radix 2/sup k/ and n-bit precision are obtained in terms of full-adder delays. The speedup with respect to radix 2 is greater than 3.3 for k/spl ges/6 and n/spl ges/64. The cost increases as a function of the radix. For the case r=64 and n=64, the increase in area with respect to r=2 is about 6.6 times plus a 512/spl times/10-bit table. The proposed scheme has been designed and verified using VHDL and a 1.2 /spl mu/m CMOS standard gate technology from MOSIS library.
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