{"title":"长精度高基数在线除法的设计","authors":"A. Tenca, M. Ercegovac","doi":"10.1109/ARITH.1999.762827","DOIUrl":null,"url":null,"abstract":"We present a design of a high-radix on-line division suitable for long precision computations. The proposed scheme uses a quotient-digit selection function based on the residual rounding and scaling of the operands. The bounds on the number of cycles and the cycle time for radix 2/sup k/ and n-bit precision are obtained in terms of full-adder delays. The speedup with respect to radix 2 is greater than 3.3 for k/spl ges/6 and n/spl ges/64. The cost increases as a function of the radix. For the case r=64 and n=64, the increase in area with respect to r=2 is about 6.6 times plus a 512/spl times/10-bit table. The proposed scheme has been designed and verified using VHDL and a 1.2 /spl mu/m CMOS standard gate technology from MOSIS library.","PeriodicalId":434169,"journal":{"name":"Proceedings 14th IEEE Symposium on Computer Arithmetic (Cat. No.99CB36336)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1999-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":"{\"title\":\"On the design of high-radix on-line division for long precision\",\"authors\":\"A. Tenca, M. Ercegovac\",\"doi\":\"10.1109/ARITH.1999.762827\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We present a design of a high-radix on-line division suitable for long precision computations. The proposed scheme uses a quotient-digit selection function based on the residual rounding and scaling of the operands. The bounds on the number of cycles and the cycle time for radix 2/sup k/ and n-bit precision are obtained in terms of full-adder delays. The speedup with respect to radix 2 is greater than 3.3 for k/spl ges/6 and n/spl ges/64. The cost increases as a function of the radix. For the case r=64 and n=64, the increase in area with respect to r=2 is about 6.6 times plus a 512/spl times/10-bit table. The proposed scheme has been designed and verified using VHDL and a 1.2 /spl mu/m CMOS standard gate technology from MOSIS library.\",\"PeriodicalId\":434169,\"journal\":{\"name\":\"Proceedings 14th IEEE Symposium on Computer Arithmetic (Cat. No.99CB36336)\",\"volume\":\"5 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1999-04-14\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"8\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings 14th IEEE Symposium on Computer Arithmetic (Cat. No.99CB36336)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ARITH.1999.762827\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings 14th IEEE Symposium on Computer Arithmetic (Cat. No.99CB36336)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ARITH.1999.762827","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
On the design of high-radix on-line division for long precision
We present a design of a high-radix on-line division suitable for long precision computations. The proposed scheme uses a quotient-digit selection function based on the residual rounding and scaling of the operands. The bounds on the number of cycles and the cycle time for radix 2/sup k/ and n-bit precision are obtained in terms of full-adder delays. The speedup with respect to radix 2 is greater than 3.3 for k/spl ges/6 and n/spl ges/64. The cost increases as a function of the radix. For the case r=64 and n=64, the increase in area with respect to r=2 is about 6.6 times plus a 512/spl times/10-bit table. The proposed scheme has been designed and verified using VHDL and a 1.2 /spl mu/m CMOS standard gate technology from MOSIS library.