VLSI costs of arithmetic parallelism: a residue reverse conversion perspective

M. Bhardwaj, T. Srikanthan, C. Clarke
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引用次数: 8

Abstract

This paper reports how VLSI cost metrics (area, delay, power) of residue reverse converters scale with the cardinality and dynamic range of moduli sets. The study uses CMAC reverse converters, reported previously by the authors to be the most efficient known to date in terms of area and delay. In all, 134 reverse converters with dynamic ranges from 32 to 120 bits and set cardinalities ranging from 4 to 20 are actually constructed and analyzed. It is seen that area, delay and power costs are cardinality insensitive once the cardinality exceeds a threshold (usually between five to eight). For cardinalities beyond this threshold, conversion costs are essentially dynamic range dependent. This insensitivity is explained in detail by noting the counterbalancing effects of the various sub-units of a CMAC reverse converter. Since practical implementations of RNS usually employ cardinalities beyond the abovementioned thresholds, the significance of this study is its conclusion that increasing the set cardinality in most implementations will have a marginal, if any, effect on VLSI reverse conversion costs.
VLSI的算术并行开销:一个残数反向转换的观点
本文报道了剩余反向转换器的VLSI成本指标(面积、延迟、功率)如何随模集的基数和动态范围的变化而变化。该研究使用了CMAC反向转换器,作者之前报道过,在面积和延迟方面,CMAC反向转换器是迄今为止已知最有效的。总共构建和分析了134个反向转换器,其动态范围从32位到120位,集合基数范围从4到20。可以看出,一旦基数超过阈值(通常在5到8之间),面积、延迟和功耗成本对基数不敏感。对于超过这个阈值的基数,转换成本基本上取决于动态范围。通过注意CMAC反向变换器的各个子单元的平衡效应,可以详细解释这种不灵敏度。由于RNS的实际实现通常使用超过上述阈值的基数,因此本研究的意义在于其结论,即在大多数实现中增加集合基数将对VLSI反向转换成本产生边际影响(如果有的话)。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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