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2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)最新文献

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A 0.2-2 GHz 12 mW multiplying DLL for low-jitter clock synthesis in highly-integrated data communication chips 一种用于高集成数据通信芯片中低抖动时钟合成的0.2-2 GHz 12mw乘法DLL
2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) Pub Date : 2002-08-07 DOI: 10.1109/ISSCC.2002.992946
R. Farjad-Rad, W. Dally, Hoik-Tiaq Ng, J. Poulton, T. Stone, R. Rathi, E. Lee, D. Huang, R. Nathan
{"title":"A 0.2-2 GHz 12 mW multiplying DLL for low-jitter clock synthesis in highly-integrated data communication chips","authors":"R. Farjad-Rad, W. Dally, Hoik-Tiaq Ng, J. Poulton, T. Stone, R. Rathi, E. Lee, D. Huang, R. Nathan","doi":"10.1109/ISSCC.2002.992946","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.992946","url":null,"abstract":"The MDLL, in 0.18 /spl mu/m CMOS, has 0.05 mm/sup 2/ active area and 200 MHz to 2 GHz speed range. The complete synthesizer, including the output clock buffers, dissipates 12 mW from a 1.8 V supply at 2.0 GHz. This MDLL architecture is used as a clock multiplier in a highly-integrated chip, and has jitter of 1.73 ps (rms) and 15.6 ps (pk-pk) at 2 GHz.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125284941","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 42
Single-chip 5.8 GHz ETC transceiver IC with PLL and demodulation circuits using SiGe HBT/CMOS 单片5.8 GHz ETC收发电路，锁相环和解调电路采用SiGe HBT/CMOS
2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) Pub Date : 2002-08-07 DOI: 10.1109/ISSCC.2002.992956
T. Masuda, K. Ohhata, N. Shiramizu, S. Hanazawa, M. Kudoh, Y. Tanba, Y. Takeuchi, H. Shimamoto, T. Nagashima, K. Washio
{"title":"Single-chip 5.8 GHz ETC transceiver IC with PLL and demodulation circuits using SiGe HBT/CMOS","authors":"T. Masuda, K. Ohhata, N. Shiramizu, S. Hanazawa, M. Kudoh, Y. Tanba, Y. Takeuchi, H. Shimamoto, T. Nagashima, K. Washio","doi":"10.1109/ISSCC.2002.992956","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.992956","url":null,"abstract":"A single-chip 5.8 GHz ETC transceiver IC with PLL and demodulator uses SiGe HBT/CMOS. The fully integrated ETC chip includes a 31 dB-gain RX stage, an ASK demodulator, and a high-precision RSSI. The PLL is constructed with a varactor-tuned LC-VCO and a low-power BiCMOS synthesizer. The TX stage incorporates a transformer-transferred single-ended PA.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"183 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121938952","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 25
A low-power RISC microprocessor using dual PLLs in a 0.13 /spl mu/m SOI technology with copper interconnect and low-k BEOL dielectric 采用双锁相环的低功耗RISC微处理器，采用0.13 /spl mu/m SOI技术，采用铜互连和低k BEOL介电
2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) Pub Date : 2002-08-07 DOI: 10.1109/ISSCC.2002.992979
S. Geissler, D. Appenzeller, E. Cohen, S. Charlebois, P. Kartschoke, P. McCormick, N. Rohrer, G. Salem, P. Sandon, B. Singer, T. von Reyn, J. Zimmerman
{"title":"A low-power RISC microprocessor using dual PLLs in a 0.13 /spl mu/m SOI technology with copper interconnect and low-k BEOL dielectric","authors":"S. Geissler, D. Appenzeller, E. Cohen, S. Charlebois, P. Kartschoke, P. McCormick, N. Rohrer, G. Salem, P. Sandon, B. Singer, T. von Reyn, J. Zimmerman","doi":"10.1109/ISSCC.2002.992979","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.992979","url":null,"abstract":"Microprocessors achieving clock frequencies >1 GHz for mobile applications require solutions to maintain long battery life. Circuit and architecture solutions for dynamic frequency switching between multiple PLLs, DC power reduction methods, and impact of low-k dielectric on timing and power are discussed.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114441692","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 27
An on-chip 100 GHz-sampling rate 8-channel sampling oscilloscope with embedded sampling clock generator 内置采样时钟发生器的片上100ghz采样率8通道采样示波器
2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) Pub Date : 2002-08-07 DOI: 10.1109/ISSCC.2002.992996
M. Takamiya, M. Mizuno, K. Nakamura
{"title":"An on-chip 100 GHz-sampling rate 8-channel sampling oscilloscope with embedded sampling clock generator","authors":"M. Takamiya, M. Mizuno, K. Nakamura","doi":"10.1109/ISSCC.2002.992996","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.992996","url":null,"abstract":"An on-chip 8-channel sampling oscilloscope macro for signal integrity checking uses a 0.13 /spl mu/m CMOS process. It contains a phase-interpolated sampling clock generator for 100GHz sampling, charge-sharing sampling heads, and ESD-tolerant decoupling capacitors for noise-immune measurement.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128102342","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 91
A 133 MHz 170 mW 10 /spl mu/A standby application processor for 3G cellular phones 用于3G手机的133 MHz 170 mW 10 /spl mu/A备用应用处理器
2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) Pub Date : 2002-08-07 DOI: 10.1109/ISSCC.2002.993086
T. Yamada, N. Irie, J. Nishimoto, Y. Kondoh, T. Nakazawa, K. Yamada, K. Tatezawa, T. Irita, S. Tamaki, H. Yagi, M. Furuyama, K. Ogura, H. Watanabe, R. Satomura, K. Hirose, F. Arakawa, T. Hattori, I. Kudo, I. Kawasaki, K. Uchiyama
{"title":"A 133 MHz 170 mW 10 /spl mu/A standby application processor for 3G cellular phones","authors":"T. Yamada, N. Irie, J. Nishimoto, Y. Kondoh, T. Nakazawa, K. Yamada, K. Tatezawa, T. Irita, S. Tamaki, H. Yagi, M. Furuyama, K. Ogura, H. Watanabe, R. Satomura, K. Hirose, F. Arakawa, T. Hattori, I. Kudo, I. Kawasaki, K. Uchiyama","doi":"10.1109/ISSCC.2002.993086","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.993086","url":null,"abstract":"An application processor for 3G cellular phones, using 0.18 /spl mu/m CMOS technology, includes a single CPU and DSP core with an on-chip 128 kB SRAM. It enables software-based 15 frames/s MPEG-4 encoding of QCIF Simple @L1 at 70 MHz and 140 mW. Standby current of the processor is <10 /spl mu/A in a partially powered standby mode using separate power lines.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132261821","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
A 1/4-inch QVGA color imaging and 3-D sensing CMOS sensor with analog frame memory 1/4英寸QVGA彩色成像和3-D传感CMOS传感器与模拟帧存储器
2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) Pub Date : 2002-08-07 DOI: 10.1109/ISSCC.2002.992292
T. Sugiyama, S. Yoshimura, R. Suzuki, H. Sumi
{"title":"A 1/4-inch QVGA color imaging and 3-D sensing CMOS sensor with analog frame memory","authors":"T. Sugiyama, S. Yoshimura, R. Suzuki, H. Sumi","doi":"10.1109/ISSCC.2002.992292","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.992292","url":null,"abstract":"A 320/spl times/240 color imaging CMOS sensor with a current-copier cell array and comparators for column-parallel processing accomplishes video rate depth acquisition. The sensor dissipates 82 mW for 3.3kframe/s 3-D sensing with 2.5 mm depth resolution, and 36 mW for 30frames/s imaging with a single CDS circuit for FPN reduction at 3.3 V.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132280401","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 33
A 2.5 V 57 MHz 15-tap SC bandpass interpolating filter with 320 MHz output sampling rate in 0.35 /spl mu/m CMOS 一个2.5 V 57 MHz 15分接SC带通插值滤波器，输出采样率为320 MHz, 0.35 /spl mu/m CMOS
2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) Pub Date : 2002-08-07 DOI: 10.1109/ISSCC.2002.992267
S. U, R. Martins, J. Franca
{"title":"A 2.5 V 57 MHz 15-tap SC bandpass interpolating filter with 320 MHz output sampling rate in 0.35 /spl mu/m CMOS","authors":"S. U, R. Martins, J. Franca","doi":"10.1109/ISSCC.2002.992267","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.992267","url":null,"abstract":"A 57 MHz SC bandpass interpolating filter with 320 Msample/s output is realized in 0.35 /spl mu/m CMOS for DDFS (direct-digital frequency synthesis) systems. 15-tap FIR response is achieved with sampling rate increase and frequency upconversion by translating 22 MHz 80 Msample/s input to 56 MHz 320 Msample/s output. Dynamic range is 69 dB (1%THD) and 61 dB (1%IM3). The filter dissipates 120 mW analog and 16 mW digital at 2.5 V supply.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"273 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133050298","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A 4.32 GOPS 1 W general-purpose DSP with an enhanced instruction set for wireless communication 一个4.32 GOPS 1w通用DSP，具有增强的无线通信指令集
2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) Pub Date : 2002-08-07 DOI: 10.1109/ISSCC.2002.992935
A. Olofsson, F. Lange
{"title":"A 4.32 GOPS 1 W general-purpose DSP with an enhanced instruction set for wireless communication","authors":"A. Olofsson, F. Lange","doi":"10.1109/ISSCC.2002.992935","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.992935","url":null,"abstract":"The authors present a 6 GOPS DSP which implements the TigerSharc architecture with an instruction set enhanced for wireless communication. It is implemented in a 0.13 μm CMOS process with 8 layers of copper interconnect and operates at 250 MHz with 1 W power dissipation under nominal conditions.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134175192","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
PicoRadios for wireless sensor networks: the next challenge in ultra-low power design 用于无线传感器网络的小无线电:超低功耗设计的下一个挑战
2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) Pub Date : 2002-08-07 DOI: 10.1109/ISSCC.2002.993005
J. Rabaey, J. Ammer, T. Karalar, Suet-Fei Li, B. Otis, M. Sheets, Tim Tuan
{"title":"PicoRadios for wireless sensor networks: the next challenge in ultra-low power design","authors":"J. Rabaey, J. Ammer, T. Karalar, Suet-Fei Li, B. Otis, M. Sheets, Tim Tuan","doi":"10.1109/ISSCC.2002.993005","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.993005","url":null,"abstract":"An untapped opportunity in the realm of wireless data lies in low data-rate (<10 kb/s) low-cost wireless transceivers, assembled into distributed networks of sensor and actuator nodes. This enables applications such as smart buildings and highways, environment monitoring, user interfaces, entertainment, factory automation, and robotics While the aggregate system processes large amounts of data, individual nodes participate in a small fraction only (typical data rates <1 kb/s). These ubiquitous networks require that the individual nodes are tiny, easily integratable into the environment, and have negligible cost. The challenges and opportunities in the design of integrated wireless sensor and actuator nodes, to be used in such self-configuring ad-hoc networks, are described. To be viable, the node must be smaller than a couple of mm/sup 3/, cost <$1, and consume <100 μW, allowing for energy scavenging from the environment.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134289483","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 423
A 35 mm film format CMOS image sensor for camera-back applications 35毫米胶片格式CMOS图像传感器，用于相机背面应用
2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) Pub Date : 2002-08-07 DOI: 10.1109/ISSCC.2002.992932
J. Hurwitz, M. Panaghiston, K. Findlater, R. Henderson, T. Bailey, A. Holmes, B. Paisley
{"title":"A 35 mm film format CMOS image sensor for camera-back applications","authors":"J. Hurwitz, M. Panaghiston, K. Findlater, R. Henderson, T. Bailey, A. Holmes, B. Paisley","doi":"10.1109/ISSCC.2002.992932","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.992932","url":null,"abstract":"A 5 V 1120×1808 pixel 35 mm film format CMOS image sensor for camera-back use, fabricated in 0.5 μm 2-poly 3-metal (2P3M) technology, includes integrated light-detection circuitry using non-destructive pixel read and consumes <50 μW. Reticle stitching is employed for the large format. Dynamic range is 66 dB and peak SNR is 55 dB.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129670059","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
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